MT48LC8M32B2

PRELIMINARY 256Mb: x32 SDRAM SYNCHRONOUS DRAM FEATURES PC100 functionality Fully synchronous; all signals registered on positive edge of system clock Internal pipelined operation; column address can www.DataSheet4U.com be changed every clock cycle Internal banks for hiding row access/precharge Programmable burst lengths: 1, 2, 4, 8, or full page Auto Precharge, includes CONCURRENT AUTO PRECHARGE, and Auto Refresh Modes Self Refresh Mode 64ms, 4,096-cycle refresh (15.6µs/row) LVTTL-compatible inputs and outputs Single +3.3V ±0.3V power supply Supports CAS latency of 1, 2, and 3 MT48LC8M32B2 - 2 Meg x 32 x 4 banks For the latest data sheet, please refer to the Micron Web site: www.micron.com/sdramds Pin Assignment (Top View) 86-Pin TSOP VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 NC VDD DQM0 WE# CAS# RAS# CS# A11 BA0 BA1 A10 A0 A1 A2 DQM2 VDD NC DQ16 VSSQ DQ17 DQ18 VDDQ DQ19 DQ20 VSSQ DQ21 DQ22 VDDQ DQ23 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 OPTIONS Configuration 8 Meg x 32 (2 Meg x 32 x 4 banks) MARKING 8M32B2 TG P F5 1 B5 1 Package 86-pin TSOP (400 mil) 86-pin TSOP (400 mil) Lead-free 90-ball FBGA (8mm x 13mm) 90-ball FBGA (8mm x 13mm) Lead-free Timing (Cycle Time) 6ns (166 MHz) 7ns (143 MHz) Operating Temperature Ra...