MPC9600

Freescale Semiconductor, Inc. MOTOROLA SEMICONDUCTOR TECHNICAL DATA Low Voltage 2.5 V and 3.3 V CMOS PLL Clock Driver The MPC9600 is a low voltage 2.5 V or 3.3 V compatible, 1:21 PLL based clock driver and fanout buffer. With output frequencies up to 200 MHz and output skews of 150 ps, the device meets the needs of the most demanding clock tree applications. Features: Multiplication of input frequency by 2, 3, 4 and 6 Distribution of output frequency to 21 outputs organized in three output banks: QA0-QA6, QB0-QB6, QC0-QC6, each fully selectable Selectable output frequency range is 50 to 100 MHz and 100 to 200 MHz Selectable input frequency range is 16.67 to 33 MHz and 25 to 50 MHz LVCMOS outputs Outputs disable to high impedance (except QFB) LVCMOS or LVPECL reference clock options 48 lead QFP packaging ±50 ps cycle-to-cycle jitter 150 ps maximum output-to-output skew 200 ps maximum static phase offset window Order Number: MPC9600/D Rev. 2, 11/2001 MPC9600 Fully integrated PLL www.DataSheet4U.com Freescale Semiconductor, Inc... 3.3 V OR 2.5 V LOW VOLTAGE CMOS PLL CLOCK DRIVER The MPC9600 is a fully LVCMOS 2.5 V or 3.3 V compatible PLL clock 48–LEAD LQFP PACKAGE driver. The MPC9600 has the capability to generate clock signals of 50 to CASE 932–03 200 MHz from clock sources of 16.67 to 50 MHz. The internal PLL is optimized for this frequency range and does not require external loop filter components. QFB provides an output for the external feedbac...