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HCTL-2021 Dataheets PDF



Part Number HCTL-2021
Manufacturers AVAGO TECHNOLOGIES
Logo AVAGO TECHNOLOGIES
Description (HCTL2017 / HCTL2021) Quadrature Decoder/Counter Interface ICs
Datasheet HCTL-2021 DatasheetHCTL-2021 Datasheet (PDF)

www.DataSheet4U.com HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs Data Sheet Description The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a qua.

  HCTL-2021   HCTL-2021


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www.DataSheet4U.com HCTL-2017 and HCTL-2021 Quadrature Decoder/Counter Interface ICs Data Sheet Description The HCTL-2021/2017 is CMOS ICs that performs the quadrature decoder, counter, and bus interface function. The HCTL-2021/2017 is designed to improve system performance in digital closed loop motion control systems and digital data input systems. It does this by shifting time intensive quadrature decoder functions to a cost effective hardware solution. The HCTL-2021/2017 consists of a quadrature decoder logic, a binary up/down state counter, and an 8-bit bus interface. The use of Schmitt-triggered CMOS inputs and input noise filters allows reliable operation in noisy environments. The HCTL-2021/2017 contains 16-bit counter and provides TLL/CMOS compatible tri-state output buffers. Operation is specified for a temperature range from –40 to +85°C at clock frequencies up to 33MHz. The HCTL-2021/2017 provides quadrature decoder output signals and cascade signals for use with many standard computer ICs. The HCTL-2021/2017 is compliant to RoHS directive and had been declared as a lead free product. Features • Interfaces Encoder to Microprocessor • 33 MHz Clock Operation • High Noise Immunity: Schmitt Trigger Inputs and Digital Noise Filter • 16-Bit Binary Up/Down Counter • Latched Outputs • 8-Bit Tristate Interface • 8 or 16-Bit Operating Modes • Quadrature Decoder Output Signals, Up/Down and Count • Cascade Output Signals, Up/Down and Count • Substantially Reduced System Software • 5V Operation (VDD – VSS) • TTL/CMOS Compatible I/O • Operating Temperature: -40°C to 85°C • 16-pin and 20-Pin Launch Pad Applications • Interface Quadrature Incremental Encoders to Microprocessors • Interface Digital Potentiometers to Digital Data Input Buses Devices Part Number HCTL-2017 HCTL-2021 Description 33 MHz clock operation. 16-bit counter. 33 MHz clock operation. 16-bit counter. Quadrature decoder output signals. Cascade output signals. Pinout PINOUT A PINOUT B www.DataSheet4U.com 1 2 3 4 5 6 7 8 D0 CLK SEL OE RST CH B CH A VSS VDD D1 D2 D3 D4 D5 D6 D7 PINOUT A 16 15 14 1 2 3 4 D0 CLK SEL OE U/D NC RST CH B CH A VSS PINOUT B VDD D1 D2 D3 20 19 18 17 Soldering and Mounting Considerations It is recommended to use manual soldering for HCTL2021/2017 launch pad devices due to the characteristics of the material used in the launch pad design that not allow wave soldering. Direct mounting on printed circuit board (PCB) only is recommended for HCTL-2021/2017 launch pad devices. Mounting gap of 1mm between the base of the launch pad and customer’s printed circuit board (PCB) is required. NOTE: Precaution is required in order to avoid bend or loose pin during product handling. 13 12 11 5 6 7 8 CNTdec 16 CNTcas 15 D4 D5 D6 D7 14 13 12 11 10 9 9 10 Package Dimensions with Tolerances Length (L) HCTL-2017 HCTL-2021 (dimension in mm) Width (W) 12.70 ± 0.5 mm 12.70 ± 0.5 mm Thickness (T) 1.67 ± 0.25 mm 1.67 ± 0.25 mm 22.86 ± 0.5 mm 27.94 ± 0.5 mm HCTL-2021 SHOWN 2 PIN DRAWING www.DataSheet4U.com Operating Characteristics Table 1. Absolute Maximum Ratings (All voltages below are referenced to VSS) Parameter DC Supply Voltage Input Voltage Storage Temperature Operating Temperature [1] Symbol VDD VIN TS TA Limits -0.3 to +6.0 -0.3 to (VDD +0.3) -40 to +100 -40 to +85 Units V V °C °C Table 2. Recommended Operating Conditions Parameter DC Supply Voltage Ambient Temperature [1] Symbol VDD TA Limits 4.5 to 5.5 -40 to +85 Units V °C Table 3. DC Characteristics VDD = 5V ± 5%; TA = -40 to 85°C Symbol VIL [2] VIH [2] VT+ VTVH IIN VOH [2] VOL [2] IOZ IDD CIN [3] COUT [3] Notes: 1. Free Air 2. In general, for any VDD between the allowable limits (+4.5V to +5.5V), VIL = 0.3VDD and VIH = 0.7VDD; typical values are VOH = VDD – 0.5V and VOL = VSS + 0.2V 3. Including package capacitance but excluding PCB capacitance. Parameter Low-Level Input Voltage High-Level Input Voltage Schmitt-Trigger Positive-Going Threshold Schmitt-Trigger Negative-Going Threshold Schmitt-Trigger Hysteresis Input Current High-Level Output Voltage Low-Level Output Voltage High-Z Output Leakage Current Quiescent Supply Current Input Capacitance Output Capacitance Condition Min 3.5 Typ Max 1.5 Unit V V V V V 3.5 1.0 1.0 VIN=VSS or VDD IOH = -3.75 mA IOL = +3.75mA VO=VSS or VDD VIN=Vss or VDD Any Input Any Output -10 -10 2.4 1.5 2.0 1 4.5 0.2 1 1 5 5 4.0 +10 µA V V µA µA PF PF 0.4 +10 10 3 w w w . D a t a S h e e t 4 U . c o m Functional Pin Description Table 4. Functional Pin Descriptions Pin Symbol VDD VSS CLK CHA CHB RST 8 2 7 6 5 HCTL-2017 HCTL-2021 16 20 10 2 9 8 7 Description Power Supply Ground CLK is a Schmitt-trigger input for the external clock signal. CHA and CHB are Schmitt-trigger inputs that accept the outputs from a quadrature-encoded source, such as incremental optical shaft encoder. Two channels, A and B, nominally 90 degrees out of phase, are required. This active low Schmitt-trigger input clears th.


IPW60R299CP HCTL-2021 HCTL2017


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