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N2SV12816FS-6K Dataheets PDF



Part Number N2SV12816FS-6K
Manufacturers Elixir
Logo Elixir
Description SDRAM
Datasheet N2SV12816FS-6K DatasheetN2SV12816FS-6K Datasheet (PDF)

www.DataSheet4U.com N2SV12816FS-6K/75B N2SV6H16FS-6K/75B 64Mb/128Mb Synchronous DRAM Features • • • • • • • Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8, Full page Programmable Wrap: Sequential or Interleave Burst Read with Single Write Operation Automatic and Controlled Precharge Command • • • • • • Dual Data Mask for byte control (x16) Auto Refresh and Self Refresh 64ms refresh peri.

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www.DataSheet4U.com N2SV12816FS-6K/75B N2SV6H16FS-6K/75B 64Mb/128Mb Synchronous DRAM Features • • • • • • • Fully Synchronous to Positive Clock Edge Four Banks controlled by BS0/BS1 (Bank Select) Programmable CAS Latency: 2, 3 Programmable Burst Length: 1, 2, 4, 8, Full page Programmable Wrap: Sequential or Interleave Burst Read with Single Write Operation Automatic and Controlled Precharge Command • • • • • • Dual Data Mask for byte control (x16) Auto Refresh and Self Refresh 64ms refresh period (4K cycle) JEDEC standard 3.3V Power Supply LVTTL compatible Package: 54-pin TSOP (II) Description The N2SV6H16FS is four-bank Synchronous DRAMs organized as 1Mbit x 16 I/O x 4 Bank, and N2SV12816FS organized as 2 Mbit x 16 I/O x 4 Bank. These synchronous devices achieve high-speed data transfer rates of up to 166MHz by employing a pipeline chip architecture that synchronizes the output data to a system clock. The device is designed to comply with all JEDEC standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, and data input/output (I/O or DQ) circuits are synchronized with the positive edge of an externally supplied clock. RAS, CAS, WE, and CS are pulsed signals which are examined at the positive edge of each externally applied clock (CK). Internal chip operating modes are defined by combinations of these signals and a command decoder initiates the necessary timings for each operation. A fourteen bit address bus accepts address data in the conventional RAS/CAS multiplexing style. Twelve row addresses (A0-A11) and two bank select addresses (BS0, BS1) are strobed with RAS. Eight column addresses (A0-A8) plus bank select addresses and A10 are strobed with CAS. Prior to any access operation, the CAS latency, burst length, and burst sequence must be programmed into the device by address inputs A0-A7, BS0, BS1 during a mode register set cycle. In addition, it is possible to program a multiple burst sequence with single write cycle for write through cache operation. Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to 166MHz is possible depending on burst length, CAS latency, and speed grade of the device. Simultaneous operation of both decks of a stacked device is allowed, depending on the operation being done. Auto Refresh (CBR) and Self Refresh operation are supported. REV 1.0 08/2006 1 The Document is a general product description and is subject to change without notice. www.DataSheet4U.com N2SV12816FS-6K/75B N2SV6H16FS-6K/75B 64Mb/128Mb Synchronous DRAM Pin Assignments for Planar Components (Top View) VDD DQ0 VDDQ DQ1 DQ2 VSSQ DQ3 DQ4 VDDQ DQ5 DQ6 VSSQ DQ7 VDD LDQM WE CAS RAS CS BS0 BS1 A10/AP A0 A1 A2 A3 VDD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 VSS DQ15 VSSQ DQ14 DQ13 VDDQ DQ12 DQ11 VSSQ DQ10 DQ9 VDDQ DQ8 VSS NC UDQM CLK CKE NC A11 A9 A8 A7 A6 A5 A4 VSS 54-pin Plastic TSOP(II) REV 1.0 08/2006 2 The Document is a general product description and is subject to change without notice. www.DataSheet4U.com N2SV12816FS-6K/75B N2SV6H16FS-6K/75B 64Mb/128Mb Synchronous DRAM Pin Description CLK CKE CS RAS CAS WE BS1, BS0 A0 - A11 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Bank Select Address Inputs DQ0-DQ15 LDQM, UDQM VDD VSS VDDQ VSSQ NC — Data Input/Output Data Mask Power supply Ground Output Power for DQs Ground for DQs No Connection — Input/Output Functional Description Symbol CLK CKE CS RAS, CAS, WE BS0, BS1 Type Input Input Input Input Input Polarity Positive Edge Active High Active Low Active Low — Function The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock. Activates the CLK signal when high and deactivates the CLK signal when low. By deactivating the clock, CKE low initiates the Power Down mode, Suspend mode, or the Self Refresh mode. CS enables the command decoder when low and disables the command decoder when high. When the command decoder is disabled, new commands are ignored but previous operations continue. When sampled at the positive rising edge of the clock, CAS, RAS, and WE define the operation to be executed by the SDRAM. Selects which bank is to be active. During a Bank Activate command cycle, A0-A11 defines the row address (RA0-RA11) when sampled at the rising clock edge. During a Read or Write command cycle, A0-A7 defines the column address (CA0-CA7) when sampled at the rising clock edge. A10 is used to invoke auto-precharge operation at the end of the burst read or write cycle. If A10 is high, auto-precharge is selected and BS0, BS1 defines the bank to be precharged. If A10 is low, autoprecharge is disabled. During a Precharge command cycle, A10 is used in conjunction with BS0, BS1 to control.


N2SV6H16FS-6K N2SV12816FS-6K N2SV6H16FS-75B


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