ABX2088

www.DataSheet4U.com ABX2088/89 Low Phase Noise XO (9.5-65MHz Output) FEATURES 19MHz to 65MHz crystal input. Output range: 9.5MHz – 65MHz Complementary outputs: PECL or LVDS output. Selectable OE Logic (enable high or enable low). Supports 2.5V or 3.3V Power Supply. Available in 16 pin TSSOP package. PIN CONFIGURATION VDD XIN XOUT DNC S2 1 2 16 15 DNC DNC GNDBUF QBAR VDDBUF Q GNDBUF GND ABX208x 3 4 5 6 7 8 14 13 12 11 10 9 DESCRIPTION The ABX2088 (PECL) and ABX2089 (LVDS) are XO ICs specifically designed to work with fundamental or 3 rd OT crystals between 19MHz and 65MHz. The selectable divide by two feature extends the operation range from 9.5MHz to 65MHz. They require very low current into the crystal resulting in better overall stability. The OE logic feature allows selection of enable high or enable low. OE N/C GND OUTPUT SELECTION AND ENABLE OE_SELECT OE_CTRL State 0 BLOCK DIAGRAM 1 (Default) 0 1 (Default) 0 (Default) 1 Tri-state Output enabled Output enabled Tri-state O Q Oscillator Amplifier S2 XQ Input selection: Bond to GND to set to “0”, bond to VDD to set to “1” No connection results to “default” setting through internal pull-up/-down. OE_CTRL: Logical states defined by PECL levels if OE_SELECT is “1” Logical states defined by CMOS levels if OE_SELECT is “0” X+ OUTPUT FREQUENCY DIVIDE BY TWO SELECTOR ABX208X Block Diagram S2 Output 0 1 Intput/2 Input 30332 Esperanza., Rancho Santa Margarita, Ca 92688 Ph: 949-546-8000 Fax: 949-546...