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HD49351HBP Dataheets PDF



Part Number HD49351HBP
Manufacturers Renesas Technology
Logo Renesas Technology
Description CDS/PGA & 10-bit A/D TG Converter
Datasheet HD49351HBP DatasheetHD49351HBP Datasheet (PDF)

www.DataSheet4U.com HD49351BP/HBP CDS/PGA & 10-bit A/D TG Converter REJ03F0110-0100Z Rev.1.0 Jul 06, 2004 Description The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351 has deleted the stripe mode, pd_mix mode, and added the 5 – 6 pulse and H_msk2 - 4 as contrasted with HD49335. There are address map and timing generator cha.

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www.DataSheet4U.com HD49351BP/HBP CDS/PGA & 10-bit A/D TG Converter REJ03F0110-0100Z Rev.1.0 Jul 06, 2004 Description The HD49351BP/HBP is a CMOS IC that provides CDS-PGA analog processing (CDS/PGA) suitable for CCD camera digital signal processing systems together with a 10-bit A/D converter and timing generator in a single chip. HD49351 has deleted the stripe mode, pd_mix mode, and added the 5 – 6 pulse and H_msk2 - 4 as contrasted with HD49335. There are address map and timing generator charts besides this specification. May be contacted to our sales department if examining the details. Functions • • • • • • Correlated double sampling PGA 10-bit ADC Timing generator Operates using only the 3 V voltage Corresponds to switching mode of power consumption and operating frequency 220 mW (Typ), maximum frequency: 36 MHz (HD49351HBP) 150 mW (Typ), maximum frequency: 25 MHz (HD49351BP) • ADC direct input mode • FBGA 65-pin package Features • Suppresses low-frequency noise, which output from CCD by the correlated double sampling. • The S/H response frequency characteristics for the reference level can be adjusted using values of external parts and registers. • High sensitivity is achieved due to the high S/N ratio and a wide dynamic range provided by a PG amplifier. • PGA, pulse timing, standby mode, etc., is achieved via a serial interface. • High precision is provided by a 10-bit-resolution A/D converter. • Difference encoded gray code can be selected as an A/D output code. It is effective in suppression of solarization (wave pattern). It is patented by Renesas. • Timing generator generates the all of pulse which are needed for CCD driving. Rev.1.0, Jul 06, 2004, page 1 of 28 HD49351BP/HBP Pin Arrangement 10 A B C D E F G H J K 9 8 7 6 5 4 3 2 1 32 31 30 29 26 24 22 XV3 XV2 XV1 DVdd3 H2 DVss4 H1 19 17 16 RG VD_i/o HD_i/o 33 34 28 27 25 23 21 20 18 15 XV4 CH1 DVdd4 1/4clk DVss4 1/2clk DVdd4 DVdd3 Reset CLK_in 35 36 CH2 CH3 38 37 XSUB CH4 40 39 SUB_PD SUB_SW 41 42 DVss3 Strob 43 45 Bias AVss 44 46 VRB ADC_in 14 14 13 DVss3 DVss3 DVdd2 12 D9 10 D7 9 D6 7 D4 5 D2 11 D8 8 D5 6 D3 4 D1 3 D0 48 49 52 55 56 57 59 61 62 2 VRM AVdd AVdd AVss test2 test1 DVdd1 41cont CDS_CS DVss1,2 47 50 51 53 54 58 60 63 64 VRT BLKC CDS_in BLKFB BLKSH DLLC MON Sdata SCK 1 ID (Top view) Notes: 1. Pin 41 outputs the STROB, pin 39 outputs the SUB_SW when pin 61 is Low. 2. Pin 41 inputs the Vgate, pin 39 inputs the ADCK when pin 61 is High. 3. 1/2 and 4clk output terminal becomes 1/3 and 1/6clk output respectively, when operating TG in 3 divided mode. Pin Description BGA Pin No. K1 J1 H1 to D2 C1 C2, C3 B1 A1 A2 B2 A3 B3 B4 A4 B5 A5 B6 A6 B7 B8 A7 PAD No. 1 2 3 to 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 Symbol ID DVss1, 2 D0 to D9 DVdd2 Dvss3 CLK_in HD_in VD_in Reset RG DVdd3 DVdd4 H1 1/2clk_o Dvss4 Dvss4 H2 1/4clk_o DVdd4 DVdd3 Description Odd/even number line detecting pulse output pin CDS Digital ground + ADC output buffer ground (0V) Digital output (D0; LSB, D9; MSB) ADC output buffer power supply (3 V) General ground for TG (0V) CLK input (max 72 MHz) HD input VD input Hardware reset (for DLL reset) Reset gate pulse output General power supply for TG (3V) H1,2 buffer power supply (3 V) H.CCD transfer pulse output-1 CLK_in 2 divided output. 3 divided output at 3 divided mode H1,2 buffer ground (0 V) H1,2 buffer ground (0 V) H.CCD transfer pulse output-2 CLK_in 4 divided output. 6 divided output at 3 divided mode H1,2 buffer power supply (3 V) General power supply for TG (3 V) I/O O — O — — I I I I O — — O O — — O O — — Analog(A) or Digital(D) D D D D D D D D D D D D D D D D D D D D 30 mA/165 pF 2 mA/10 pF 30 mA/165 pF 2 mA/10 pF Schmitt trigger 3 mA/10 pF 2 mA/10 pF Remarks 2 mA/10 pF Rev.1.0, Jul 06, 2004, page 2 of 28 HD49351BP/HBP Pin Description (cont.) BGA Pin No. A8 A9 A10 B10 B9 C10 C9 D9 D10 E9 E10 F9 F10 G9 H9 G10 H10 K10 J10 J9 K9 K8 J8 K7 K6 J7 J6 PAD No. 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Symbol XV1 XV2 XV3 XV4 CH1 CH2 CH3 CH4 XSUB SUB_SW SUB_PD STROB DVss3 AVss ADC_in BIAS VRB VRT VRM Avdd BLK_C CDS_in AVdd BLKFB BLKSH AVss Test2 Description V.CCD transfer pulse output-1 V.CCD transfer pulse output-2 V.CCD transfer pulse output-3 V.CCD transfer pulse output-4 Read out pulse output-1 Read out pulse output-2 Read out pulse output-3 Read out pulse output-4 Pulse output for electronic shutter SUB voltage control output-1. Input the ADCK when 61 pin is Hi SUB voltage control output-2 Flash control output. Input Vgate at Hi of 61pin General ground for TG (0 V) Analog ground (0 V) A/D converter input pin Bias standard resistance (33 kΩ for Gnd) ADC bottom standard voltage (0.1 µF for Gnd) ADC top standard voltage (0.1 µF for Gnd) ADC middle standard voltage (0.1 µF for Gnd) Analog power supply (3 V) Black level C pin (1000pF for Gnd) CDS input pin Analog power supply (3 V) Black level FB pin (1 µF between BLKFB and BLKSH) Black level S/H pin Analog ground (.


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