ICS487-25

www.DataSheet4U.com ICS487-25 Quad PLL for DTV Features Packaged in 16-pin TSSOP Available in Pb-free packaging Replaces multiple crystals and oscillators Input crystal or clock frequency of 27 MHz Zero ppm frequency synthesis error Duty cycle of 45/55 Operating voltage of 3.3 V Advanced, low power CMOS process Description The ICS487-25 generates five high-quality, high-frequency clock outputs. It is designed to replace crystals and crystal oscillators in DTV applications. Using ICS’ patented Phase Locked Loop (PLL) techniques, the device runs from a lower frequency crystal or clock input. Because there is zero ppm frequency synthesis error on the audio clocks, the audio will remain locked to the video. Block Diagram VDD 3 2 S1:0 PLL1 ACLK 20M PLL2 48M PLL3 33.0M 27 MHz clock or crystal input X1/ICLK X2 Crystal Oscillator/ Clock Buffer PLL4 24.576M External capacitors may be required. 3 GND PDTS (all outputs and PLLs) MDS 487-25 A I nt eg ra te d Cir c uit S ys t em s l 1 52 5 Race Stree t, Sa n Jose, CA 95 126 l Revision 050604 tel (4 08) 297-1 201 l w ww. i c s t . c o m ICS487-25 Quad PLL for DTV Pin Assignment X1/ICLK S0 S1 48M VDD GND 20M 24.576M 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 X2 VDD PDTS GND VDD GND 33.0M ACLK ACLK Output Selection Table S1 0 0 1 1 S0 0 1 0 1 ACLK (MHz) 18.432 16.9344 12.288 18.432 Note: When S1 and S0 are switched, all other output clocks will remain stable throughout the transition. 16 pin (173 mil) TSSOP...