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ICS421004I-01 Dataheets PDF



Part Number ICS421004I-01
Manufacturers ICS
Logo ICS
Description CRYSTAL-TO-HSTL FREQUENCY SYNTHESIZER
Datasheet ICS421004I-01 DatasheetICS421004I-01 Datasheet (PDF)

www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS8421004I-01 FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER FEATURES • Four HSTL outputs (VOHmax = 1.4V) • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) • Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8.

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www.DataSheet4U.com PRELIMINARY Integrated Circuit Systems, Inc. ICS8421004I-01 FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER FEATURES • Four HSTL outputs (VOHmax = 1.4V) • Selectable crystal oscillator interface or LVCMOS/LVTTL single-ended input • Supports the following output frequencies: 156.25MHz, 125MHz, 62.5MHz • VCO range: 560MHz - 680MHz • RMS phase jitter @ 156.25MHz, using a 25MHz crystal (1.875MHz - 20MHz): 0.44ps (typical) • Power supply modes: Core/Output 3.3V/1.8V 2.5V/1.8V • -40°C to 85°C ambient operating temperature GENERAL DESCRIPTION The ICS8421004I-01 is a 4 output HSTL Synthesizer optimized to generate Ethernet HiPerClockS™ reference clock frequencies and is a member of the HiPerClocksTM family of high performance clock solutions from ICS. Using a 25MHz 18pF parallel resonant crystal, the following frequencies can be generated based on the 2 frequency select pins (F_SEL[1:0]): 156.25MHz, 125MHz and 62.5MHz. The ICS8421004I-01 uses ICS’ 3rd generation low phase noise VCO technology and can achieve 1ps or lower typical rms phase jitter, easily meeting Ethernet jitter requirements. The ICS8421004I-01 is packaged in a small 24-pin TSSOP package. ICS FREQUENCY SELECT FUNCTION TABLE M Divider Value 25 25 25 25 N Divider Value 4 5 10 not used M/N Divider Value 6.25 5 2.5 Output Frequency (25MHz Ref.) 156.25 125 62.5 not used PIN ASSIGNMENT nQ1 Q1 VDDO Q0 nQ0 MR nPLL_SEL nc VDDA F_SEL0 VDD F_SEL1 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 nQ2 Q2 VDDO Q3 nQ3 GND VDD nXTAL_SEL TEST_CLK GND XTAL_IN XTAL_OUT F_SEL1 F_SEL0 0 0 1 1 0 1 0 1 BLOCK DIAGRAM F_SEL[1:0] nPLL_SEL Pulldown Pulldown ICS8421004I-01 2 TEST_CLK Pulldown 25MHz 1 1 F_SEL[1:0] 0 0 ÷4 0 1 ÷5 10 11 ÷10 Not Used 24-Lead TSSOP 4.40mm x 7.8mm x 0.92mm package body G Package Q0 Top View nQ0 Q1 nQ1 XTAL_IN OSC XTAL_OUT nXTAL_SEL Pulldown 0 Phase Detector VCO 0 Q2 nQ2 M = 25 (fixed) Q3 nQ3 MR Pulldown The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice. 8421004AGI-01 www.icst.com/products/hiperclocks.html 1 REV. A MACH 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8421004I-01 FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER Type Description Differential output pair. HSTL interface levels. Output supply pins. Differential output pair. HSTL interface levels. Active HIGH Master Reset. When logic HIGH, the internal dividers are reset causing the true outputs Qx to go low and the inver ted outputs nQx Pulldown to go high. When logic LOW, the internal dividers and the outputs are enabled. LVCMOS/LVTTL interface levels. Selects between the PLL and TEST_CLK as input to the dividers. When Pulldown LOW, selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL Bypass). LVCMOS/LVTTL interface levels. No connect. Analog supply pin. Pulldown Frequency select pins. LVCMOS/LVTTL interface levels. Core supply pin. Parallel resonant cr ystal interface. XTAL_OUT is the output, XTAL_IN is the input. Power supply ground. Pulldown LVCMOS/LVTTL clock input. Selects between cr ystal or TEST_CLK inputs as the the PLL Reference Pulldown source. Selects XTAL inputs when LOW. Selects TEST_CLK when HIGH. LVCMOS/LVTTL interface levels. Differential output pair. HSTL interface levels. Differential output pair. HSTL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 22 4, 5 6 Name nQ1, Q1 VDDO Q0, nQ0 MR Output Power Ouput Input 7 8, 18 9 10, 12 11 13, 14 15, 19 16 17 20, 21 23, 24 nPLL_SEL nc VDDA F_SEL0, F_SEL1 VDD XTAL_OUT, XTAL_IN GND TEST_CLK nXTAL_SEL nQ3, Q3 Q2, nQ2 Input Unused Power Input Power Input Power Input Input Output Output NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol CIN RPULLDOWN Parameter Input Capacitance Input Pulldown Resistor Test Conditions Minimum Typical 4 51 Maximum Units pF kΩ 8421004AGI-01 www.icst.com/products/hiperclocks.html 2 REV. A MACH 29, 2005 PRELIMINARY Integrated Circuit Systems, Inc. ICS8421004I-01 FEMTOCLOCKS™ CRYSTAL-TOHSTL FREQUENCY SYNTHESIZER 4.6V -0.5V to VDD + 0.5V 50mA 100mA 70°C/W (0 mps) -65°C to 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VDD Inputs, VI Outputs, IO Continuous Current Surge Current Package Thermal Impedance, θJA Storage Temperature, TSTG TABLE 3A. POWER SUPPLY DC .


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