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MT48H16M16LF

Micron Technology

(MT48H16M16LF / MT48H16M32LF) 16 Meg x 32 Mobile SDRAM

www.DataSheet4U.com 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H32M16LF – 8 Meg x 16 x 4 b...


Micron Technology

MT48H16M16LF

File Download Download MT48H16M16LF Datasheet


Description
www.DataSheet4U.com 512Mb: 32 Meg x 16, 16 Meg x 32 Mobile SDRAM Features Mobile SDRAM MT48H32M16LF – 8 Meg x 16 x 4 banks MT48H16M32LF/LG – 4 Meg x 32 x 4 banks Features Endur-IC™ technology Fully synchronous; all signals registered on positive edge of system clock VDD = 1.7–1.95V; VDDQ = 1.7–1.95V Internal, pipelined operation; column address can be changed every clock cycle Four internal banks for concurrent operation Programmable burst lengths: 1, 2, 4, 8, and continuous1 Auto precharge, includes concurrent auto precharge Auto refresh and self refresh modes LVTTL-compatible inputs and outputs On-chip temperature sensor to control refresh rate Partial-array self refresh (PASR) Deep power-down (DPD) Selectable output drive (DS) Table 1: DQ Bus Width Options VDD/VDDQ – 1.8V/1.8V Row size option – Standard addressing option – Reduced page-size option Configuration – 32 Meg x 16 (8 Meg x 16 x 4 banks) – 16 Meg x 32 (4 Meg x 32 x 4 banks) Plastic “green” packages – 54-Ball VFBGA (10mm x 11.5mm) – 90-Ball VFBGA (10mm x 13mm) Timing – cycle time – 7.5ns at CL = 3 – 8ns at CL = 3 Power – Standard IDD2P/IDD7 – Low IDD2P/IDD7 Operating temperature range – Commercial (0°C to +70°C) – Industrial (–40°C to +85°C) Design revision Marking H LF LG3, 4 32M16 16M32 CJ5 CM3 -75 -8 None L None IT :A Configuration Addressing JEDECStandard Option 4 BA0, BA1 A0–A12 A0–A9 A0–A12 A0–A8 Reduced Page-Size Option2 4 BA0, BA1 – – A0–A13 A0–A7 Architectu...




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