IDT74SSTUBF32866B

www.DataSheet4U.com DATASHEET 25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2 CONFIDENTIAL IDT74SSTUBF32866B Description This 25-bit 1:1 or 14-bit 1:2 configurable registered buffer is designed for 1.7-V to 1.9-V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8-V CMOS drivers that have been optimized to drive the DDR-II DIMM load. IDT74SSTUBF32866B operates from a differential clock (CLK and CLK). Data are registered at the crossing of CLK going high, and CLK going low. The C0 input controls the pinout configuration of the 1:2 pinout from A configuration (when low) to B configuration (when high). The C1 input controls the pinout configuration from 25-bit 1:1 (when low) to 14-bit 1:2 (when high). A - Pair Configuration (C01 = 0, C11 = 1 and C02 = 0, C12 = 1) Parity that arrives one cycle after the data input to which it applies is checked on the PAR_IN of the first register. The second register produces to PPO and QERR signals. The QERR of the first register is left floating. The valid error information is latched on the QERR output of the second register. If an error occurs QERR is latched low for two cycles or until RESET is low. B - Single Configuration (C0 = 0, C1 = 0) The device supports low-power standby operation. When the RESET input (RESET) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are a...