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STK25CA8 Dataheets PDF



Part Number STK25CA8
Manufacturers Simtek
Logo Simtek
Description 128K x 8 AutoStore nvSRAM CMOS Nonvolatile Static RAM Module
Datasheet STK25CA8 DatasheetSTK25CA8 Datasheet (PDF)

www.DataSheet4U.com STK25CA8 128K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Module FEATURES • Nonvolatile Storage without Battery Problems • Directly Replaces 128K x 8 Static RAM, BatteryBacked RAM or EEPROM • 35ns and 45ns Access Times • STORE to EEPROM Initiated by AutoStore™ on Power Down • RECALL to SRAM on Power Restore • 22mA ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to EEPROM • 100-Year Data Retention Over Full Commer.

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www.DataSheet4U.com STK25CA8 128K x 8 AutoStore™ nvSRAM QuantumTrap™ CMOS Nonvolatile Static RAM Module FEATURES • Nonvolatile Storage without Battery Problems • Directly Replaces 128K x 8 Static RAM, BatteryBacked RAM or EEPROM • 35ns and 45ns Access Times • STORE to EEPROM Initiated by AutoStore™ on Power Down • RECALL to SRAM on Power Restore • 22mA ICC at 200ns Cycle Time • Unlimited READ, WRITE and RECALL Cycles • 1,000,000 STORE Cycles to EEPROM • 100-Year Data Retention Over Full Commercial Temperature Range • Commercial and Industrial Temperatures • 32-Pin 600 mil Dual In-Line Module DESCRIPTION The Simtek STK25CA8 is a fast static RAM with a nonvolatile, electrically erasable PROM element incorporated in each static memory cell. The SRAM can be read and written an unlimited number of times, while independent nonvolatile data resides in the EEPROM. Data transfers from the SRAM to the EEPROM (the STORE operation) can take place automatically on power down using charge stored in system capacitance. Transfers from the EEPROM to the SRAM (the RECALL operation) take place automatically on restoration of power. BLOCK DIAGRAM A15 A16 A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 MODULE DECODER EEPROM ARRAY 512 x 512 STORE STATIC RAM ARRAY 512 x 512 RECALL PIN CONFIGURATIONS NC A16 A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 VCC STORE/ RECALL CONTROL POWER CONTROL VCC A15 NC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 ROW DECODER 32 - 600 mil Dual In-Line Module PIN NAMES INPUT BUFFERS COLUMN I/O COLUMN DEC A0 - A16 W DQ0 - DQ7 Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 5V) Ground A0 A1 A2 A3 A4 A10 E G E W G VCC VSS August 1999 6-1 STK25CA8 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . –55°C to 125°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . –65°C to 150°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS COMMERCIAL SYMBOL ICC1 b (VCC = 5.0V ± 10%) INDUSTRIAL UNITS MIN MAX 140 125 20 22 18 9 ±2 ±10 2.2 VSS – .5 2.4 0.4 0 70 –40 VCC + .5 0.8 2.2 VSS – .5 2.4 0.4 85 MIN MAX 150 133 25 25 20 9 ±2 ±10 VCC + .5 0.8 mA mA mA mA mA mA µA µA V V V V °C tAVAV = 35ns tAVAV = 45ns All Inputs Don’t Care, VCC = max W ≥ (VCC – 0.2V) All Others Cycling, CMOS Levels All Inputs Don’t Care E ≥ (VCC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = – 4mA IOUT = 8mA NOTES PARAMETER Average VCC Current Average VCC Current During STORE Average VCC Current at tAVAV = 200ns Average VCC Current During AutoStore™ Cycle VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage Operating Temperature ICC2c ICC3b ICC4 ISBd IILK IOLK VIH VIL VOH VOL TA c Note b: ICC1 and ICC3 are dependent on output loading and cycle rate. The specified values are obtained with outputs unloaded. Note c: ICC and ICC are the average currents required for the duration of the respective STORE cycles (tSTORE ) . 2 4 Note d: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .See Figure 1 5.0V 480 Ohms OUTPUT 255 Ohms CAPACITANCEe SYMBOL CIN COUT PARAMETER Input Capacitance Output Capacitance (TA = 25°C, f = 1.0MHz) MAX 20 28 UNITS pF pF CONDITIONS ∆V = 0 to 3V ∆V = 0 to 3V 30 pF INCLUDING SCOPE AND FIXTURE Note e: These parameters are guaranteed but not tested. Figure 1: AC Output Loading August 1999 6-2 STK25CA8 SRAM READ CYCLES #1 & #2 SYMBOLS NO. 1 2 3 4 5 6 7 8 9 10 11 PARAMETER #1, #2 tELQV tAVAVf tAVQVg tGLQV tAXQXg tELQX tEHQZh tGLQX tGHQZh tELICCHe tEHICCLd, e Alt. tACS tRC tAA tOE tOH tLZ tHZ tOLZ tOHZ tPA tPS C.


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