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STK1744 Dataheets PDF



Part Number STK1744
Manufacturers Simtek
Logo Simtek
Description 32K x 8 AutoStore nvSRAM
Datasheet STK1744 DatasheetSTK1744 Datasheet (PDF)

www.DataSheet4U.com STK1744 nvTime™ 32K x 8 AutoStore™ nvSRAM with Real-Time Clock FEATURES • Data Integrity of Simtek nvSRAM Combined with Full-Featured Real-Time Clock • Stand-Alone Nonvolatile Memory and TimeKeeping Solution—No Other Parts Required • No Batteries to Fail • Fast 25ns, 35ns and 45ns Access Times • Software- and AutoStore™-Controlled Nonvolatile Cycles • Year 2000 Compliant with Leap Year Compensation • 24-Hour BCD Format • 100-Year Data Retention over Full Industrial Temperat.

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www.DataSheet4U.com STK1744 nvTime™ 32K x 8 AutoStore™ nvSRAM with Real-Time Clock FEATURES • Data Integrity of Simtek nvSRAM Combined with Full-Featured Real-Time Clock • Stand-Alone Nonvolatile Memory and TimeKeeping Solution—No Other Parts Required • No Batteries to Fail • Fast 25ns, 35ns and 45ns Access Times • Software- and AutoStore™-Controlled Nonvolatile Cycles • Year 2000 Compliant with Leap Year Compensation • 24-Hour BCD Format • 100-Year Data Retention over Full Industrial Temperature Range • Full 30-Day RTC Operation on Each Power Loss • Single 5V ± 10% Power Supply DESCRIPTION PRELIMINARY The Simtek STK1744 DIP module houses 256Kb of nonvolatile static RAM, a real-time clock (RTC) with crystal and a high-value capacitor to support systems that require high reliability and ease of manufacturing. READ and WRITE access to all RTC functions and the memory is the same as a conventional x 8 SRAM. The highest eight addresses of the RAM support clock registers for centuries, years, months, dates, days, hours, minutes and seconds. Independent data resides in the integral Nonvolatile Elements at all times. Automatic RECALL on power up transfers the Nonvolatile Elements data to the SRAM, while an automatic STORE on power down transfers SRAM data to the Nonvolatile Elements. A software RECALL and STORE are also possible on user command. nvTime™ allows unlimited READ and WRITE accesses to SRAM, unlimited RECALLs and 106 STOREs. BLOCK DIAGRAM QUANTUM TRAP 512 x 512 VCC STORE/ RECALL CONTROL PIN CONFIGURATIONS A14 A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 A5 A6 A7 A8 A9 A11 A12 A13 A14 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 ROW DECODER STORE STATIC RAM ARRAY 512 x 512 RECALL POWER CONTROL SOFTWARE DETECT A0 - A13 VCC W A13 A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 28 - 600 DIP Module (See application note for surface mount) INPUT BUFFERS COLUMN I/O COLUMN DEC RTC PIN NAMES A0 - A14 W Address Inputs Write Enable Data In/Out Chip Enable Output Enable Power (+ 5V) Ground A0 A1 A2 A3 A4A10 MUX A0 A14 G E W DQ0 - DQ7 E G VCC VSS January 2003 1 Document Control # ML0020 rev 0.0 STK1744 ABSOLUTE MAXIMUM RATINGSa Voltage on Input Relative to Ground . . . . . . . . . . . . . .–0.5V to 7.0V Voltage on Input Relative to VSS . . . . . . . . . . –0.6V to (VCC + 0.5V) Voltage on DQ0-7 . . . . . . . . . . . . . . . . . . . . . . –0.5V to (VCC + 0.5V) Temperature under Bias . . . . . . . . . . . . . . . . . . . . . . –55°C to 85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . –65°C to 85°C Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1W DC Output Current (1 output at a time, 1s duration) . . . . . . . . 15mA Note a: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. DC CHARACTERISTICS SYMBOL ICC b 1 (VCC = 5.0V ± 10%) COMMERCIAL MIN MAX 97 80 70 3 10 30 25 22 1.5 ±1 ±5 2.2 VSS – .5 2.4 0.4 0 70 – 40 VCC + .5 0.8 2.2 VSS – .5 2.4 0.4 85 INDUSTRIAL MIN MAX 100 85 70 3 10 31 26 23 1.5 ±1 ±5 VCC + .5 0.8 UNITS mA mA mA mA mA mA mA mA mA µA µA V V V V °C tAVAV = 25ns tAVAV = 35ns tAVAV = 45ns All Inputs Don’t Care, VCC = max W ≥ (V CC – 0.2V) All Others Cycling, CMOS Levels tAVAV = 25ns, E ≥ VIH tAVAV = 35ns, E ≥ VIH tAVAV = 45ns, E ≥ VIH E ≥ (V CC – 0.2V) All Others VIN ≤ 0.2V or ≥ (VCC – 0.2V) VCC = max VIN = VSS to VCC VCC = max VIN = VSS to VCC, E or G ≥ VIH All Inputs All Inputs IOUT = – 4mA IOUT = 8mA NOTES PARAMETER Average VCC Current ICC ICC 2 b Average VCC Current during STORE Average VCC Current at tAVAV = 200ns 5V, 25°C, Typical Average VCC Current (Standby, Cycling TTL Input Levels) VCC Standby Current (Standby, Stable CMOS Input Levels) Input Leakage Current Off-State Output Leakage Current Input Logic “1” Voltage Input Logic “0” Voltage Output Logic “1” Voltage Output Logic “0” Voltage Operating Temperature 3 ISB c 1 ISB c 2 IILK IOLK VIH VIL VOH VOL TA Note b: ICC and ICC are dependent on output loading and cycle rate. The specified values are obtained at minimum cycle with outputs unloaded. 1 3 Note c: E ≥ VIH will not produce standby current levels until any nonvolatile cycle in progress has timed out. AC TEST CONDITIONS Input Pulse Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0V to 3V Input Rise and Fall Times . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ≤ 5ns Input and Output Timing Reference Levels . . . . . . . . . . . . . . . 1.5V Output Load . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . See Figure 1 5.0V CAPACITANCEd SYMBOL CIN COUT PARAMETER Input Capacitance.


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