Document
www.DataSheet4U.com
ST22T064-A
Smartcard 32-Bit RISC MCU with 64 Kbytes EEPROM & USB 2.0 Full Speed Device Controller
DATA BRIEF
PRODUCT FEATURES
I I I I
I I I
CLOCK AND POWER MANAGEMENT VOLTAGE AND CLOCK FREQUENCY SENSORS ADVANCED MEMORY PROTECTION – – – Memory Protection Unit for application firewalling and peripheral access control Domain switching securely controlled by protected Context Stack Native/Java, Code/Data memory attributes with 128-byte granularity Java stack with both 16 and 32-bit accesses User and Supervisor mode stacks Security Context Stack
32-BIT RISC CPU WITH 24-BIT LINEAR MEMORY ADDRESSING 228 KBYTES USER ROM 16 KBYTES USER RAM 64 KBYTES USER EEPROM DUAL INSTRUCTION SET, JAVACARD™ AND NATIVE 4-STAGE PIPELINE 16 GENERAL PURPOSE 32-BIT REGISTERS, AND SPECIAL REGISTERS 4 MASKABLE INTERRUPT LEVELS SUPERVISOR AND USER MODES
32-BIT RISC CPU
I I I I I
I
FOUR WORKING STACKS – – –
USB 2.0 FULL SPEED DEVICE CONTROLLER WITH ON CHIP CLOCK RECOVERY
I I I I I
UP TO 12Mbits/s BANDWIDTH 16 DYNAMICALLY CONFIGURABLE ENDPOINTS ALL USB TRANSFER MODES SUPPORTED ISO / USB MODE DETECTION CCID AND ISO 7816-12 COMPLIANT
Figure 1. Delivery Form
4 4
SECURITY
I
4
4
CPU SECURITY INSTRUCTIONS – – Dedicated instructions for DES and Triple DES implementation Dedicated instructions (Multiply and Accumulate) for efficient implementation of modular arithmetic and elliptic curves based cryptosystems CRC instruction (ISO 3309 16-bit Checksum)
SO20 Micromodule Wafer
–
I I I I
ENCRYPTION CO-PROCESSOR CPU DPA/SPA COUNTERMEASURES RANDOM NUMBER GENERATOR EEPROM FLASH PROGRAMMING MODE
October 2004
For further information contact your local ST sales office.
1/7
7
www.DataSheet4U.com
ST22T064-A
CRYPTOGRAPHIC LIBRARY The Crypto Library is provided as a separate ROM area with an access through a unique entry point. This library provides optimized -for the SmartJ core- and secured implementation of the following features:
I
MEMORY
I
HIGHLY RELIABLE CMOS EEPROM TECHNOLOGY – – – Error Correction Code for single bit fail within a 32-bit word 10 years data retention, 500,000 Erase/ Write cycles endurance 1 to 128 bytes Erase or Program in 2 ms typical Dual memory buses for data and instruction Byte, Short (2) and Word (4) load and store Address auto-increment
ASYMMETRICAL ALGORITHMS – – – RSA signature/verification Prime number generation (up to 1024-bit) RSA key computation (up to 2048-bit) SHA-1 – –
I I
HIGH PERFORMANCE MEMORY –
I
HASH FUNCTION – SYMMETRICAL ALGORITHMS – DES, Triple DES, AES
I
CRYPTOGRAPHY PERFORMANCE The following table provides the cryptographic performances of the ST22T064-A based on ST Crypto Library. Table 1. Preliminary Cryptographic Performances
Algorithm RSA 1024 bits RSA 2048 bits DES TDES(3) SHA-1 AES-128 Function Signature with CRT Signature without CRT(2) Verification (e=0x10001) Signature with CRT Signature without CRT Verification (e=0x10001) Triple Single Triple (with keys loaded) 512-bit Block Encryption includ.