Document
www.DataSheet4U.com
SEPTEMBER 2006
XRT84L38
OCTAL T1/E1/J1 FRAMER
REV. 1.0.1
GENERAL DESCRIPTION
The XRT84L38 is an eight-channel 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framing controller. The XRT84L38 contains an integrated DS1/E1/J1 framer which provides DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers, and can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function including 3 HDLC controllers to support V5.2. Each Transmit HDLC controller encapsulates contents of the Transmit HDLC buffers into LAPD Message frames. Each Receive HDLC controller extracts payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and writes it into the Receive HDLC buffer. Each framer also contains a Transmit
and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames Likewise, a Receive Overhead output data port permits Data Link Terminal Equipment direct access to the Data Link bits of the inbound T1/E1/J1 frames. The XRT84L38 fully meets all of the latest T1/E1/J1 specifications: ANSI T1/E1.107-1988, ANSI T1/ E1.403-1995, ANSI T1/E1.231-1993, ANSI T1/ E1.408-1990, AT&T TR 62411 (12-90) TR54016, and ITU G-703, G.704, G706 and G.733, AT&T Pub. 43801, and ETS 300 011, 300 233, JT G.703, JT G.704, JT G706, I.431. Extensive test and diagnostic functions include Loop-backs, Boundary scan, Pseudo Random bit sequence (PRBS) test pattern generation, Performance Monitor, Bit Error Rate (BER) meter, forced error insertion, and LAPD unchannelized data payload processing according to ITU-T standard Q.921. Applications and Features (next page)
FIGURE 1. XRT84L38 8-CHANNEL DS1 (T1/E1/J1) FRAMER
External Data Link Controller
Local PCM Highway
XRT84L38
1 of 8-channels
8
Tx Overhead In
Rx Overhead Out
TxPOS 8 TxNEG 8 TxLineCLK 8
8 DS1/E1 Channels 1.544/2.048 MHz
XRT83L38
TPOS TNEG TCLK1
Tx Serial Data In
2-Frame Slip Buffer Elastic Store
Tx Framer
Tx Encoder LIU Interface LLB LB
Tx1
Twisted Pair
Tx Serial Clock
Rx1 RxPOS 8 RxNEG 8 RxLineCLK 8 RPOS RNEG RCLK1 µP Interface Tx8
ST-BUS
Twisted Pair
8
Rx Serial Data Out
2-Frame Slip Buffer Elastic Store
Rx Framer
Rx Encoder LIU Interface LIU & Loopback Control
Rx Serial Clock
PRBS Generator & Analyser
Performance Monitor
HDLC (LAPD) Controller & 96-byte Buffer
8kHz sync OSC Signaling & Alarms JTAG DMA Interface
Rx8
Microprocessor Interface
Back Plane 1.544-16.384 Mbit/s
8-CH T1/E1/LIU Host Mode
4 WR ALE_AS RD RDY_DTACK
3 Interrupt D[7:0] A[6:0] Channel Select
System (Terminal) Side
Memory
Intel/Motorola µP Configuration, Control & Status Monitor
Line Side
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • (510) 668-7000 • FAX (510) 668-7017 • www.exar.com
XRT84L38
OCTAL T1/E1/J1 FRAMER APPLICATIONS
REV. 1.0.1
• High-Density T1/E1/J1 interfaces for Multiplexers, Switches, LAN Routers and Digital Modems • SONET/SDH terminal or Add/Drop multiplexers (ADMs) • T1/E1/J1 add/drop multiplexers (MUX) • Channel Service Units (CSUs): T1/E1/J1 and Fractional T1/E1/J1 • Digital Access Cross-connect System (DACs) • Digital Cross-connect Systems (DCS) • Frame Relay Switches and Access Devices (FRADS) • ISDN Primary Rate Interfaces (PRA) • PBXs and PCM channel bank • T3 channelized access concentrators and M13 MUX • Wireless base stations • ATM equipment with integrated DS1 interfaces • Multichannel DS1 Test Equipment • T1/E1/J1 Performance Monitoring • Voice over packet gateways • Routers
FEATURES
• Eight independent, full duplex DS1 Tx and Rx Framers • Two 512-bit (two-frame) elastic store, PCM frame slip buffers (FIFO) on TX and Rx provide up to 8.192 MHz
asynchronous back plane connections with jitter and wander attenuation
• Supports input PCM and signaling data at 1.544, 2.048, 4.096 and 8.192 Mbits. Also supports 4-channel
multiplexed 12.352/16.384 (HMVIP/H.100) Mbit/s on the back plane bus
• Programmable output clocks for Fractional T1/E1/J1 • Supports Channel Associated Signaling (CAS) • Supports Common Channel Signalling (CCS) • Supports ISDN Primary Rate Interface (ISDN PRI) signaling • Extracts and inserts robbed bit signaling (RBS) • 3 independent HDLC Controllers for Receive and Transmit on a per channel basis • Each HDLC controller contains two 96-BYTE buffers • Timeslot assignable HDLC • V5.1 and V5.2 Interface • 8-bit Intel/Motorola μP and MIPS Power PC interfaces for configuration, control and status monitoring • Parallel search algorithm for fast frame synchronization • Wide choice of T1 framing structures: D4, ESF, SLC®96, TIDM and N-Frame (non-framing) • Direct access to D and E channels for fast transmission of data link information • PRBS and QRSS generation and detection
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XRT84L38
REV. 1.0.1
OC.