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Freescale Semiconductor Data Sheet: Technical Data
Document Number: MCF5485EC Rev. 3, 03/2007
MCF5485
TEPBGA–388
MCF5485 Integrated Microprocessor Electrical Characteristics
This chapter contains electrical specification tables and reference timing diagrams for the MCF5485 microprocessor. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of the MCF5485. MCF548X Family Features: • ColdFire V4e Core – Limited superscalar V4 ColdFire processor core – Up to 200MHz peak internal core frequency (308 MIPS (Dhrystone 2.1) @ 200 MHz) – Harvard architecture – 32-Kbyte instruction cache – 32-Kbyte data cache – Memory Management Unit (MMU) – Floating point unit (FPU) • Internal master bus (XLB) arbiter • 32-bit double data rate (DDR) synchronous DRAM (SDRAM) controller – 66–133 MHz operation • Version 2.2 peripheral component interconnect (PCI) bus • Flexible multi-function external bus (FlexBus) • Communications I/O subsystem – Intelligent 16 channel DMA controller, with support for – Dedicated DMA channels for receive and transmit on all subsystem peripheral interfaces – Up to two (2) 10/100 Mbps fast Ethernet controllers (FECs) – Universal serial bus (USB) version 2.0 device controller – Up to four (4) programmable serial controllers (PSCs) for UART, USART, modem, codec, and IrDA 1.1 interfaces – I2C peripheral interface – Two (2) controller area network 2.0B controllers – DMA Serial Peripheral Interface (DSPI) • Optional Cryptography accelerator module – DES/3DES block cipher – AES block cipher – RC4 stream cipher – MD5/SHA-1/SHA-256/HMAC hashing – Random Number Generator • 32-Kbyte system SRAM • System integration unit (SIU) – Interrupt controller – Watchdog timer – Two (2) 32-bit slice timers – Up to four (4) 32-bit general-purpose timers – General-purpose I/O ports multiplexed with peripheral pins • Debug and test features – ColdFire background debug mode (BDM) port – JTAG/ IEEE 1149.1 test access port • PLL and clock generator – 30 to 66.67 MHz input frequency range
© Freescale Semiconductor, Inc., 2007. All rights reserved.
ColdFire V4e Core FPU, MMU EMAC 32K D-cache 32K I-Cache
DDR SDRAM PLL Interface
FlexBus Interface
XL Bus Arbiter XL Bus
Memory Controller
FlexBus Controller
System Integration Unit
Controller
Interface
Watchdog Timer Slice Timers x 2
Cryptography Accelerator*** Crypto R/W
PCI 2.2 Controller
Perpheral I/O Interface & Ports
GP Timers x 4 Slave Bus DMA
32K System SRAM Read Write DMA
XL Bus Read/Write
FlexCAN x2
Multi-Channel DMA Master Bus Interface & FIFOs CommBus
PCI Interface Communications I/O Subsystem & FIFOs
DSPI
I2C
PSC x 4
FEC1
FEC22
USB 2.0 DEVICE1
USB 2.0 Perpheral Communications I/O Interface & Ports PHY1
Figure 1. MCF548X Block Diagram
1 2
Available in MCF5485, MCF5484, MCF5483 and MCF5482 devices. Available in MCF5485, MCF5484, MCF5481 and MCF5480 devices. 3 Available in MCF5485, MCF5483, and MCF5481 devices.
MCF5485 Integrated Microprocessor Electrical Characteristics, Rev. 3 2 Freescale Semiconductor
PCI I/O Interface & Ports
Interrupt
Master/Slave
Table of Contents
1 2 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4 2.1 Operating Temperatures . . . . . . . . . . . . . . . . . . . . . . . . .4 2.2 Thermal Resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 DC Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Hardware Design Considerations . . . . . . . . . . . . . . . . . . . . . . .6 4.1 PLL Power Filtering. . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 4.2 Supply Voltage Sequencing and Separation Cautions . .6 4.3 General USB Layout Guidelines . . . . . . . . . . . . . . . . . . .8 4.4 USB Power Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Output Driver Capability and Loading. . . . . . . . . . . . . . . . . . .10 PLL Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . .11 Reset Timing Specifications . . . . . . . . . . . . . . . . . . . . . . . . . .12 FlexBus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 8.1 FlexBus AC Timing Characteristics. . . . . . . . . . . . . . . .13 SDRAM Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 SDR SDRAM AC Timing Characteristics . . . . . . . . . . . . . . . .15 10.1 DDR SDRAM AC Timing Characteristics . . . . . . . . . . .18 PCI Bus. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Fast Ethernet AC Timing Specifications . . . . . . . . . . . . . . . . .23 12.1 MII/7-WIRE Interface Timing Specs . . . . . . . . . . . . . . .23 12.2 MII Transmit Signal Timing . . . . . . . . . . . . . . . . . . . . . .24 12.3 MII Async Inputs Signal Timing (CRS, COL) . . . . . . . .24 12.4 MII S.