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MBM29PL32TM Dataheets PDF



Part Number MBM29PL32TM
Manufacturers Fujitsu Media Devices
Logo Fujitsu Media Devices
Description (MBM29PL32TM/BM) FLASH MEMORY CMOS 32 M (4M X 8/2M X 16) BIT MirrorFlash
Datasheet MBM29PL32TM DatasheetMBM29PL32TM Datasheet (PDF)

www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20907-3E FLASH MEMORY CMOS 32 M (4M × 8/2M × 16) BIT MirrorFlashTM* MBM29PL32TM/BM 90/10 s DESCRIPTION The MBM29PL32TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words by 16 bits. The MBM29PL32TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operatio.

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www.DataSheet4U.com FUJITSU SEMICONDUCTOR DATA SHEET DS05-20907-3E FLASH MEMORY CMOS 32 M (4M × 8/2M × 16) BIT MirrorFlashTM* MBM29PL32TM/BM 90/10 s DESCRIPTION The MBM29PL32TM/BM is a 32M-bit, 3.0 V-only Flash memory organized as 4M bytes by 8 bits or 2M words by 16 bits. The MBM29PL32TM/BM is offered in 48-pin TSOP(1) and 48-ball FBGA. The device is designed to be programmed in-system with the standard 3.0 V VCC supply. 12.0 V VPP and 5.0 V VCC are not required for write or erase operations. The devices can also be reprogrammed in standard EPROM programmers. (Continued) s PRODUCT LINE UP Part No. VCC Max Address Access Time Max CE Access Time Max Page Read Access Time MBM29PL32TM/BM 90 3.0 V to 3.6 V 90 ns 90 ns 25 ns 10 3.0 V to 3.6 V 100 ns 100 ns 30 ns s PACKAGES 48-pin plastic TSOP (1) 48-ball plastic FBGA (FPT-48P-M19) * : MirrorFlashTM is a trademark of Fujitsu Limited. (BGA-48P-M20) Notes : • Programming in byte mode ( × 8) is prohibited. • Programming to the address that already contains data is prohibited. (It is mandatory to erase data prior to overprogram on the same address.) MBM29PL32TM/BM90/10 (Continued) The standard MBM29PL32TM/BM offers access times of 90 ns, allowing operation of high-speed microprocessors without wait states. To eliminate bus contention the devices have separate chip enable (CE), write enable (WE), and output enable (OE) controls. The MBM29PL32TM/BM supports command set compatible with JEDEC single-power-supply EEPROMS standard. Commands are written into the command register. The register contents serve as input to an internal statemachine which controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for the programming and erase operations. Reading data out of the devices is similar to reading from 5.0 V and 12.0 V Flash or EPROM devices. The MBM29PL32TM/BM is programmed by executing the program command sequence. This will invoke the Embedded Program AlgorithmTM which is an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. Erase is accomplished by executing the erase command sequence. This will invoke the Embedded Erase AlgorithmTM which is an internal algorithm that automatically preprograms the array if it is not already programmed before executing the erase operation. During erase, the device automatically times the erase pulse widths and verifies proper cell margin. The device also features a sector erase architecture. The sector mode allows each sector to be erased and reprogrammed without affecting other sectors. All sectors are erased when shipped from the factory. The device features single 3.0 V power supply operation for both read and write functions. Internally generated and regulated voltages are provided for the program and erase operations. A low VCC detector automatically inhibits write operations on the loss of power. The end of program or erase is detected by Data Polling of DQ7, by the Toggle Bit feature on DQ6. Once the end of a program or erase cycle has been completed, the devices internally return to the read mode. Fujitsu Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of quality, reliability, and cost effectiveness. The devices electrically erase all bits within a sector simultaneously via hot-hole assisted erase. The words are programmed one word at a time using the EPROM programming mechanism of hot electron injection. 2 MBM29PL32TM/BM90/10 s FEATURES • 0.23 µm Process Technology • Single 3.0 V read, program and erase Minimizes system level power requirements • Industry-standard pinouts 48-pin TSOP (1) (Package suffix: TN - Normal Bend Type) 48-ball FBGA(Package suffix: PBT) • Minimum 100,000 program/erase cycles • High performance Page mode Fast 8 bytes / 4 words access capability • Sector erase architecture Eight 8K byte and sixty-three 64K byte sectors Eight 4K word and sixty-three 32K word sectors Any combination of sectors can be concurrently erased. Also supports full chip erase • Boot Code Sector Architecture T = Top sector B = Bottom sector • HiddenROM 256 bytes / 128 words of HiddenROM, accessible through a “HiddenROM Entry” command sequence Factory serialized and protected to provide a secure electronic serial number (ESN) • WP/ACC input pin At VIL, allows protection of outermost two 8K bytes / 4K words sectors, regardless of sector protection/unprotection status At VACC, increases program performance • Embedded EraseTM* Algorithms Automatically pre-programs and erases the chip or any sector • Embedded ProgramTM* Algorithms Automatically writes and verifies data at specified address • Data Polling and Toggle Bit feature for detection of program or erase cycle completion • Ready/Busy output (RY/BY) Hardware method for detection of program or erase cycle completion • Automatic sleep mode When addresses remain stable, automatically switches themselves to low power mode.


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