K4S510432M

K4S510432M Preliminary CMOS SDRAM 512Mbit SDRAM 32M x 4bit x 4 Banks Synchronous DRAM LVTTL www.DataSheet4U.com Revision 0.2 Dec. 2001 Samsung Electronics reserves the right to change products or specification without notice. Rev. 0.2 Dec. 2001 K4S510432M Revision History Revision 0.0 (Mar. 2001) Revision 0.1 (Aug. 2001) Defined target DC characteristics. Preliminary CMOS SDRAM Revision 0.2 (Dec. 2001) Changed "Target" to "Preliminary". Redefined DC characteristics. Rev. 0.2 Dec. 2001 K4S510432M 32M x 4Bit x 4 Banks Synchronous DRAM FEATURES JEDEC standard 3.3V power supply LVTTL compatible with multiplexed address Four banks operation MRS cycle with address key programs -. CAS latency (2 & 3) -. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave) All inputs are sampled at the positive going edge of the system clock. Burst read single-bit write operation DQM for masking Auto & self refresh 64ms refresh period (8K cycle) Part No. K4S510432M-TC/TL75 K4S510432M-TC/TL1H K4S510432M-TC/TL1L Preliminary CMOS SDRAM GENERAL DESCRIPTION The K4S510432M is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 33,554,432 words by 4 bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies all...