Document
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T431616D/E
SDRAM
FEATURES
Fast access time: 5/6/7 ns • Fast clock rate: 200/166/143 MHz • Self refresh mode: standard and low power • Internal pipelined architecture • 512K word x 16-bit x 2-bank • Programmable Mode registers - CAS# Latency: 1, 2, or 3 - Burst Length: 1, 2, 4, 8, or full page - Burst Type: interleaved or linear burst - Burst stop function • Individual byte controlled by LDQM and UDQM • Auto Refresh and Self Refresh • 4096 refresh cycles/64ms • CKE power down mode • JEDEC standard +3.3V±0.3V power supply • Interface: LVTTL • 50-pin 400 mil plastic TSOP II package • 60-ball, 6.4x10.1mm VFBGA package • Lead Free Package available for both TSOP II and VFBGA •Low Operating Current for T431616E
1M x 16 SDRAM
512K x 16bit x 2Banks Synchronous DRAM
GRNERAL DESCRIPTION
The T431616D/E SDRAM is a high-speed CMOS synchronous DRAM containing 16 Mbits. It is internally configured as a dual 512K word x 16 DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). Each of the 512K x 16 bit banks is organized as 2048 rows by 256 columns by 16 bits. Read and write accesses to the SDRAM are burst oriented; accesses start at a selected location and continue for a programmed number of locations in a programmed sequence. Accesses begin with the registration of a BankActivate command which is then followed by a Read or Write command. The T431616D/E provides for programmable Read or Write burst lengths of 1, 2, 4, 8, or full page, with a burst termination option. An auto precharge function may be enabled to provide a self-timed row precharge that is initiated at the end of the burst sequence. The refresh functions, either Auto or Self Refresh are easy to use. By having a programmable mode register, the system can choose the most suitable modes to maximize its performance. These devices are well suited for applications requiring high memory bandwidth and particularly well suited to high performance PC applications
Key Specifications
T431616D/E tCK3 tRAS tAC3 tRC
Clock Cycle time(min.) Row Active time(max.) Access time from CLK(max.) Row Cycle time(min.)
-5/6/7
5/6/7ns 35/42/42 ns 4.5/5/5.5 ns 48/54/63 ns
ORDERING INFORMATION
Part Number T431616D-5S/C T431616D-5SG/CG T431616D-6S/C T431616D-6SG/CG T431616D-7S/C T431616D-7SG/CG T431616E-7S/C T431616E-7SG/CG G : indicates Lead Free Package Frequency 200MHz 200MHz 166MHz 166MHz 143MHz 143MHz 143MHz 143MHz Package TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA TSOP II / VFBGA
TM Technology Inc. reserves the right P. 1 to change products or specifications without notice.
Publication Date: FEB. 2007 Revision: A
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T431616D/E
PIN ARRANGEMENT BGA (Top View)
2 3 4 5 6 7
TSOP-II (Top View)
V DD 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5 0 P IN T S O P (II) (4 0 0 m il x 8 2 5 m il) (0 .8 m m P IN P IT C H ) 50 49 48 47 46 45 44 43 42 41 40 39 38 .