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T431616C Dataheets PDF



Part Number T431616C
Manufacturers TMT
Logo TMT
Description 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM
Datasheet T431616C DatasheetT431616C Datasheet (PDF)

tm • • • • • TE CH T431616C SDRAM FEATURES 3.3V power supply Clock cycle time : 6 / 7 ns Dual banks operation LVTTL compatible with multiplexed address All inputs are sampled at the positive going edge of system clock • Burst Read Single-bit Write operation • DQM for masking • Auto refresh and self refresh • 32ms refresh period (2K cycle) • MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) • Available.

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tm • • • • • TE CH T431616C SDRAM FEATURES 3.3V power supply Clock cycle time : 6 / 7 ns Dual banks operation LVTTL compatible with multiplexed address All inputs are sampled at the positive going edge of system clock • Burst Read Single-bit Write operation • DQM for masking • Auto refresh and self refresh • 32ms refresh period (2K cycle) • MRS cycle with address key programs - CAS Latency ( 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) • Available package type : - 50 pin TSOP(II)/lead-free • Operating temperature : - 0 ~ +70 °C 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM GRNERAL DESCRIPTION The T431616C is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits , fabricated with high performance CMOS technology . Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle . Range of operating frequencies , programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth , high performance memory system applications. ORDERING INFORMATION PART NO. CLOCK CYCLE TIME 6ns 6ns 7ns 7ns MAX FREQUENCY PACKAGE TSOP-II TSOP-II Lead-free TSOP-II TSOP-II Lead-free OPERATING TEMPERATURE T431616C-6S T431616C-6SG T431616C-7S T431616C-7SG 166 MHz 166 MHz 143 MHz 143 MHz 0 ~ +70 °C 0 ~ +70 °C 0 ~ +70 °C 0 ~ +70 °C TM Technology Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm VDD DQ0 DQ1 V SSQ DQ2 DQ3 VDDQ DQ4 DQ5 V SSQ DQ6 DQ7 VDDQ LD Q M WE CAS RAS CS BA A 1 0 /A P A0 A1 A2 A3 VDD TE CH T431616C PIN ARRANGEMENT (TSOP-II Top View) 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 5 0 P IN T S O P ( II) ( 4 0 0 m il x 8 2 5 m il) ( 0 .8 m m P IN P IT C H ) 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 V ss D Q 15 D Q 14 V SSQ D Q 13 D Q 12 VDDQ D Q 11 D Q 10 V SSQ DQ9 DQ8 VDDQ N .C /R F U UDQM CLK CKE N .C A9 A8 A7 A6 A5 A4 V ss TM Technology Inc. reserves the right P. 2 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm TE CH T431616C BLOCK DIAGRAM I/O Control LW E Bank Select D ata Input Register LDQ M Row Decoder Row Buffeer Refresh Counter Sense AMP 512K x 16 Output Buffer D Qi Address Register CLK 512K x 16 A DD LCBR LRAS Col. Buffer Colum n Decoder Latency & Burst Length LCKE LRAS LCBR LW E LCAS Tim ing Register Program m ing R egister LW CB R LDQ M CLK CK E CS RA S CA S WE L(U)DQ M TM Technology Inc. reserves the right P. 3 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm PIN CLK TE CH T431616C PIN DESCRIPTION NAME System Clock Chip Select INPUT FUNCTION Active on the positive going edge to sample all input. Disables or enables device operation by masking or enabling all input except CLK,CKE and L(U)DQM Masks system clock to freeze operation from the next clock cycle. CS CKE Clock Enable CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. A0 ~ A10/AP BA Address Bank Select Address Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA10,column address : CA0 ~ CA7 Selects bank to be activated during row address latch time. Select bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK RAS Row Address Strobe with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK CAS Column Address Strobe with CAS low. Enables column access . WE L(U)DQM DQ0 ~ DQ15 VDD/VSS VDDQ/VSSQ Write Enable Data Input/Output Mask Data Input/Output Enables write operation and row precharge. Latches data in starting from CAS , WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when L(U)DQM active. Data inputs/outputs are multiplexed on the same pins. Power Supply/Ground Power and ground for the input buffers and the core logic. Data Output Power/Ground No Connection/Reserved for Future Use Isolated power supply and ground for the output buffers to provide improved noise immunity. This pin is recommended to be left No Connection on the device. N.C/RFU TM Technology Inc. reserves the right P. 4 to change products or specifications without notice. Publication Date: AUG. 2004 Revision: A tm Parameter TE CH T431616C ABSOLUTE MAXIMUM RATINGS Symbol VIN,VOUT VDD,VDDQ Iout PD TOPR Tstg Value -1.0 to 4.6 -1.0 to 4.6 50 1 0 to +70 -55 to +125 Unit V V mA W °C °C Voltage on Any Pin Relative To Vss Supply Voltage Relative To Vss Short circuit Output Current Power Dissipation Operating Temperature Storage Temperature Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be .


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