T431616B

tm TE CH T431616B SDRAM FEATURES +2.7 to +3.6V power supply Dual banks operation LVTTL compatible with multiplexed address All inputs are sampled at the positive going edge of system clock Burst Read Single-bit Write operation DQM for masking Auto refresh and self refresh 32ms refresh period (2K cycle) MRS cycle with address key programs - CAS Latency ( 1 & 2 & 3 ) - Burst Length ( 1 , 2 , 4 , 8 & full page) - Burst Type (Sequential & Interleave) Available package type in 50 pin TSOP(II) 1M x 16 SDRAM 512K x 16bit x 2Banks Synchronous DRAM GRNERAL DESCRIPTION The T431616B is 16,777,216 bits synchronous high data rate Dynamic RAM organized as 2 x 524,288 words by 16 bits , fabricated with high performance CMOS technology . Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clockcycle . Range of operating frequencies , programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth , high performance memory system applications. and 60-pin CSP ORDERING INFORMATION PART NO. T431616B-20S T431616B-20C T431616B-10S T431616B-10C MAX FREQUENCY 50 MHz 50 MHz 100 MHz 100 MHz PACKAGE TSOP-II CSP TSOP-II CSP Taiwan Memory Technology, Inc. reserves the right P. 1 to change products or specifications without notice. Publication Date: JUL. 2001 Revision:A tm V DD DQ0 DQ1 V SSQ DQ2 DQ3 V DDQ DQ4 DQ5 V SSQ DQ6 DQ7 V DDQ LDQM WE CAS RAS CS BA A1...