Document
Data Sheet
1.5 Ω On Resistance, ±15 V/+12 V/±5 V, iCMOS, Quad SPST Switches
ADG1411/ADG1412/ADG1413
06815-001
FEATURES
1.5 Ω on resistance 0.3 Ω on-resistance flatness 0.1 Ω on-resistance match between channels Continuous current per channel
LFCSP: 250 mA TSSOP: 190 mA Fully specified at +12 V, ±15 V, and ±5 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP AEC-Q100 qualified for automotive applications
APPLICATIONS
Automated test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio signal routing Video signal routing Communications systems Relay replacement
GENERAL DESCRIPTION
The ADG1411/ADG1412/ADG1413 are monolithic complementary metal-oxide semiconductor (CMOS) devices containing four independently selectable switches designed on an iCMOS® process. iCMOS (industrial CMOS) is a modular manufacturing process combining high voltage CMOS and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no previous generation of high voltage devices has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size.
The on-resistance profile is very flat over the full analog input range, ensuring excellent linearity and low distortion when switching signals.
iCMOS construction ensures ultralow power dissipation, making the devices ideally suited for portable and batterypowered instruments.
The ADG1411/ADG1412/ADG1413 contain four independent single-pole/single-throw (SPST) switches. The ADG1411 and
FUNCTIONAL BLOCK DIAGRAM
S1 IN1
D1
S2 IN2
D2
ADG1411
S3 IN3
D3
S4 IN4
D4
S1 IN1
D1
S2 IN2
D2
ADG1412
S3 IN3
D3
S4 IN4
D4
S1 IN1
D1
S2 IN2
D2
ADG1413
S3 IN3
D3
S4 IN4
D4
SWITCHES SHOWN FOR A LOGIC 1 INPUT.
Figure 1.
ADG1412 differ only in that the digital control logic is inverted. The ADG1411 switches are turned on with Logic 0 on the appropriate control input, whereas the ADG1412 switches are turned on with Logic 1. The ADG1413 has two switches with digital control logic similar to that of the ADG1411; the logic is inverted on the other two switches. Each switch conducts equally well in both directions when on and has an input signal range that extends to the supplies. In the off condition, signal levels up to the supplies are blocked.
The ADG1413 exhibits break-before-make switching action for use in multiplexer applications. Inherent in the design is low charge injection, which results in minimum transients when the digital inputs are switched.
PRODUCT HIGHLIGHTS
1. 2.6 Ω maximum on resistance over temperature. 2. Minimum distortion. 3. Ultralow power dissipation: <0.03 μW. 4. 16-lead TSSOP and 16-lead, 4 mm × 4 mm LFCSP.
Rev. D
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ADG1411/ADG1412/ADG1413
TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Product Highlights ........................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3
±15 V Dual Supply ....................................................................... 3 +12 V Single Supply ..................................................................... 4 ±5 V Dual Supply ......................................................................... 5
REVISION HISTORY
1/2020—Rev. C to Rev. D Change to Features Section ............................................................. 1 Changes to Leakage Currents Parameter, Table 1 ........................ 3 Changes to Leakage Currents Parameter, Table 2 ........................ 4 Changes to Leakage Currents Parameter, Table 3 ........................ 5.