Document
August 2005 rev 1.3 LCD Panel EMI Reduction IC
Features
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P2042A
wide reduction of EMI of
down stream clock and data
FCC approved method of EMI attenuation. Provides up to 15dB of EMI suppression. Generates a low EMI spread spectrum clock of the input frequency. Input frequency range: 30MHz to 110MHz. Optimized for 32.5MHz, 54MHz, 65MHz and 108MHz pixel clock frequencies. Internal loop filter minimizes external components and board space. Eight selectable high spread ranges up to ± 1.9%. SSON# control pin for spread spectrum enable and disable options. Low cycle-to-cycle jitter. 3.3V ± 0.3V operating range. Low power CMOS design. Supports most mobile graphic accelerator and LCD timing controller specifications. Available in 8-pin SOIC and TSSOP Packages.
dependent signals. The P2042A allows significant system cost savings by reducing the number of circuit board layers ferrite beads, regulations. The P2042A uses the most efficient and optimized modulation profile approved by the FCC and is implemented in a proprietary all digital method. The P2042A modulates the output of a single PLL in order to “spread” the bandwidth of a synthesized clock, and more importantly, decreases the peak amplitudes of its harmonics. This results in significantly lower system EMI compared to the typical narrow band signal produced by oscillators and most frequency generators. Lowering EMI by increasing a signal’s bandwidth is called ‘spread spectrum clock generation’. shielding and other passive components that are traditionally required to pass EMI
Product Description
The P2042A is a versatile spread spectrum frequency modulator designed specifically for digital flat panel applications. The P2042A reduces electromagnetic interference (EMI) at the clock source, allowing system
Applications
The P2042A is targeted towards digital flat panel applications for notebook PCs, palm-size PCs, office automation equipments and LCD monitors.
Block Diagram
VDD SR0 CP1 CP0 SSON#
Modulation CLKIN Frequency Divider Feedback Divider
PLL
Phase Detector
Loop Filter
VCO
Output Divider ModOUT
VSS
Alliance Semiconductor 2575 Augustine Drive • Santa Clara, CA • Tel: 408.855.4900 • Fax: 408.855.4999 • www.alsc.com
Notice: The information in this document is subject to change without notice.
August 2005 rev 1.3
Pin Configuration
CLKIN CP0 CP1 VSS
1 2 3 4 8 7 6 5
P2042A
VDD SR0 ModOUT SSON#
P2042A
Pin Description Pin#
1 2 3 4 5 6
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Pin Name
CLKIN CP0 CP1 VSS SSON# ModOUT SR0 VDD
Type
I I I P I O I P
Description
External reference frequency input. Connect to externally generated reference signal. Digital logic input used to select charge pump current. This pin has an internal pull-up resistor. Refer Modulation Selection Table. Digital logic input used to select charge pump current. This pin has an internal pull-up resistor. Refer Modulation Selection Table. Ground to entire chip. Connect to system ground. Digital logic input used to enable Spread Spectrum function (Active LOW). Spread Spectrum function enabled when LOW, disabled when HIGH. This pin has an internal pull-low resistor. Spread spectrum clock output. Digital logic input used to select Spreading Range. This pin has an internal pull-up resistor. Power supply for the entire chip
7 8
Modulation Selection CP0
0 0 0 0 1 1 1 1
CP1
0 0 1 1 0 0 1 1
SR0
0 1 0 1 0 1 0 1
Spreading Range (±%) 32.5MHz
0.56 1.94 1.36 1.92 1.24 1.91 0.91 1.47
54MHz
1.05 1.68 1.05 1.68 0.81 1.29 0.45 0.71
65MHz
1.00 1.56 1.00 1.56 0.66 1.02 0.34 0.54
81MHz
0.98 1.48 0.92 1.48 0.40 0.74 0.05 0.36
108MHz
0.80 1.22 0.67 1.06 0.27 0.43 0.15 0.21
Modulation Rate (KHz)
(FIN /40) * 62.49 KHz
LCD Panel EMI Reduction IC
Notice: The information in this document is subject to change without notice.
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August 2005 rev 1.3
Spread Spectrum Selection
P2042A
The Modulation Selection Table defines the possible spread spectrum options. The optimal setting should minimize system EMI to the fullest without affecting system performance. The spreading is described as a percentage deviation of the center frequency. (Note: The center frequency is the frequency of the external reference input on CLKIN, pin1). For example, P2042A is designed for high-resolution, flat panel applications and is able to support an XGA (1024 x 768) flat panel operating at 65MHz (FIN) clock speed. A spreading selection of CP0=0, CP1=1 and SR0=0 provides a percentage deviation of ±1.00% from FIN. This results in the frequency on ModOUT being swept from 65.65 to 64.35MHz at a modulation rate of 101.54KHz. Refer Modulation Selection Table. The example in the following illustration is a common EMI reduction method for a notebook LCD panel and has already been implemented by most of the leading OEM and mobile graphic accelerator manufacturers.
Application Schematic for Mobile LCD Graphics Controllers
65MHz from graphics accelerator
1
CLKIN CP0 CP1 VSS
VDD SR0 ModOUT SSON#.