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MC68HC908GT8 Dataheets PDF



Part Number MC68HC908GT8
Manufacturers Freescale Semiconductor
Logo Freescale Semiconductor
Description Microcontroller
Datasheet MC68HC908GT8 DatasheetMC68HC908GT8 Datasheet (PDF)

MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet M68HC08 Microcontrollers www.DataSheet4U.com MC68HC908GT16 Rev. 5.0 04/2007 freescale.com MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks o.

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MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet M68HC08 Microcontrollers www.DataSheet4U.com MC68HC908GT16 Rev. 5.0 04/2007 freescale.com MC68HC908GT16 MC68HC908GT8 MC68HC08GT16 Data Sheet To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current. Your printed copy may be an earlier revision. To verify you have the latest information available, refer to: http://freescale.com Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. This product incorporates SuperFlash® technology licensed from SST. © Freescale Semiconductor, Inc., 2007. All rights reserved. MC68HC908GT16 • MC68HC908GT8 • MC68HC08GT16 Data Sheet, Rev. 5.0 Freescale Semiconductor 3 Revision History The following revision history table summarizes changes contained in this document. For your convenience, the page number designators have been linked to the appropriate location. Revision History (Sheet 1 of 2) Date March, 2002 Revision Level N/A Original release 7.2 Features — Corrected third bulleted item to reflect ±4 percent variability Figure 15-1. Forced Monitor Mode (Low) — Reworked for clarity Figure 15-2. Forced Monitor Mode (High) — Reworked for clarity May, 2002 Figure 15-3. Standard Monitor Mode — Reworked for clarity 1.0 Table 15-1. Monitor Mode Signal Requirements and Options — Reworked for clarity Figure 12-4. Port A I/O Circuit — Reworked to correct pullup resistor Figure 12-11. Port C I/O Circuit — Reworked to correct pullup resistor Figure 12-15. Port D I/O Circuit — Reworked to correct pullup resistor Figure 2-2. Control, Status, and Data Registers — Corrected ESCI arbiter data register (SCIADAT) to reflect read-only status June, 2002 2.0 Figure 14-19. ESCI Arbiter Control Register (SCIACTL) — Corrected address location designator from $0018 to $000A Figure 14-20. ESCI Arbiter Data Register (SCIADAT) — Corrected address location designator from $0019 to $000B Reformatted to meet current publications standards 1.5.6 ADC Reference Pins (VREFH and VREFL) — Corrected connections 2.6.3 Flash Page Erase Operation — Updated procedure 2.6.4 Flash Mass Erase Operation — Updated procedure 2.6.5 Flash Program/Read Operation — Updated procedure 2.6.6 Flash Block Protection — Description updated for clarity 3.3.5 Conversion — Updated for clarity 3.6.3 ADC Voltage Reference High Pin (VREFH) — Corrected connections 3.0 (Continued on next page) 3.6.4 ADC Voltage Reference Low Pin (VREFL) — Corrected connections 3.7.1 ADC Status and Control Register — Updated description of the COCO bit Chapter 4 Configuration Register (CONFIG) — Updated COP tmeout selections Chapter 4 Configuration Register (CONFIG) — Updted SSREC bit usage Chapter 5 Computer Operating Properly (COP) Module — Updated timeout selections Figure 5-1. COP Block Diagram — Updated illustration for clarity Table 6-1. Instruction Set Summary — Updated definitions for STOP and WAIT Figure 7-9. Code Example for Switching Clock So.


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