M2040

Integrated Circuit Systems, Inc. Product Data Sheet M2040 FIN_SEL1 GND AUTO DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC 27 26 25 24 23 22 21 20 19 FREQUENCY TRANSLATION PLL WITH AUTOSWITCH PIN ASSIGNMENT (9 x 9 mm SMT) GENERAL DESCRIPTION The M2040 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock protection, frequency translation and jitter attenuation in fault tolerant computing applications. It features dual differential inputs with two modes of input selection: manual and automatic upon clock failure. The clock multiplication ratios and output divider ratio are pin selectable. External loop components allow the tailoring of PLL loop response. FEATURES ◆ Integrated SAW (surface acoustic wave) delay line; VCSO frequency of 400.00 or 533.3334 MHz;* outputs VCSO frequency or half; pin-configurable dividers ◆ Loss of Lock (LOL) indicator output ◆ Narrow Bandwidth control input (NBW Pin); Initialization (INIT) input overrides NBW at power-up ◆ Dual reference clock inputs support LVDS, LVPECL, LVCMOS, LVTTL ◆ Automatic (non-revertive) reference clock reselection upon clock failure; controlled PLL slew rate ensures normal system operation during reference reselection www.DataSheet4U.com FIN_SEL0 MR_SEL REF_ACK LOL NBW VCC DNC DNC DNC 28 29 30 31 32 33 34 35 36 M2040 (Top View) 18 17 16 15 14 13 12 11 10 P_SEL INIT nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND Figure 1: Pin Assignment Example Input / Output Frequency Combinations ...