W3EG7266S-AD4

White Electronic Designs W3EG7266S-AD4 -BD4 PRELIMINARY* 512MB – 64Mx72 DDR SDRAM UNBUFFERED ECC w/PLL FEATURES Double-data-rate architecture DDR200, DDR266, DDR300 and DDR400 JEDEC design specifications Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Power supply: VCC = VCCQ = +2.5V ± 0.2V (100, 133 and 166MHz) * This data sheet describes a product that is not fully qualified or characterized and is subject to change without notice. DESCRIPTION The W3EG7266S is a 64Mx72 Double Data Rate SDRAM memory module based on 512Mb DDR SDRAM components. The module consists of nine 64Mx8 DDR SDRAMs in 66 pin TSOP packages mounted on a 200 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. www.DataSheet4U.com VCC = VCCQ = +2.6V ± 0.1V (200MHz) JEDEC standard 200 pin SO-DIMM package Package height options: AD4: 35.05 mm (1.38”) BD4: 31.75 mm (1.25”) NOTE: Consult factory for availability of: Lead-Free Products Vendor source control options Industrial temperature options OPERATING FREQUENCIES DDR400@CL=3 Clock ...