W3EG264M72AFSRXXXD3

White Electronic Designs W3EG264M72AFSRxxxD3 ADVANCED* 1GB – 2x64Mx72 DDR SDRAM REGISTERED ECC w/PLL, FBGA FEATURES Double-data-rate architecture DDR200, DDR266 and DDR333: JEDEC design specifications Phase-lock loop (PLL) clock driver to reduce loading Bi-directional data strobes (DQS) Differential clock inputs (CK & CK#) Programmable Read Latency 2,2.5 (clock) Programmable Burst Length (2,4,8) Programmable Burst type (sequential & interleave) Edge aligned data output, center aligned data input Auto and self refresh Serial presence detect Dual Rank www.DataSheet4U.com DESCRIPTION The W3EG264M72AFSR is a 2x64Mx72 Double Data Rate SDRAM memory module based on 256Mb DDR SDRAM components. The module consists of thirtysix 64Mx4, in FBGA packages mounted on a 184 pin FR4 substrate. Synchronous design allows precise cycle control with the use of system clock. Data I/O transactions are possible on both edges and Burst Lengths allow the same device to be useful for a variety of high bandwidth, high performance memory system applications. * This product is under development, is not qualified or characterized and is subject to change or cancellation without notice. Power supply: VCC 2.5V ± 0.2V JEDEC standard 184 pin DIMM package Package height option: Low-profile: 30.48mm (1.20") Consult factory for availability of lead-free products. NOTE: Consult factory for availability of: RoHS compliant products Vendor source control options Industrial temperature option OPERATING ...