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NS ESIG D N EW CT F O R PR O D U D E E ND UT E Data Sheet O M M U B S TI T C E S R 0 9582 NOT SSIBLE X PO
®
X9269
Single Supply/Low Power/256-Tap/2-Wire Bus
April 17, 2007 FN8173.4
Dual Digitally-Controlled (XDCP™) Potentiometers
FEATURES • Dual–Two Separate Potentiometers • 256 Resistor Taps/Pot–0.4% Resolution • 2-Wire Serial Interface for Write, Read, and Transfer Operations of the Potentiometer Single Supply Device • Wiper Resistance, 100Ω Typical VCC = 5V • 4 Nonvolatile Data Registers for Each Potentiometer • Nonvolatile Storage of Multiple Wiper Positions • Power-on Recall. Loads Saved Wiper Position on Power-up. • Standby Current < 5µA Max • 50kΩ, 100kΩ Versions of End to End Pot Resistance • 100 yr. Data Retention • Endurance: 100,000 Data Changes per Bit per Register • 24-Lead SOIC, 24-Lead TSSOP • Low Power CMOS www.DataSheet4U.com • Power Supply VCC = 2.7V to 5.5V • Pb-Free Plus Anneal Available (RoHS Compliant) FUNCTIONAL DIAGRAM
DESCRIPTION The X9269 integrates 2 digitally controlled potentiometer (XDCP) on a monolithic CMOS integrated circuit. The digital controlled potentiometer is implemented using 255 resistive elements in a series array. Between each element are tap points connected to the wiper terminal through switches. The position of the wiper on the array is controlled by the user through the 2-Wire bus interface. Each potentiometer has associated with it a volatile Wiper Counter Register (WCR) and a four nonvolatile Data Registers that can be directly written to and read by the user. The contents of the WCR controls the position of the wiper on the resistor array though the switches. Powerup recalls the contents of the default Data Register (DR0) to the WCR. The XDCP can be used as a three-terminal potentiometer or as a two terminal variable resistor in a wide variety of applications including control, parameter adjustments, and signal processing.
VCC
RH0
RH1
2-Wire Bus Interface
Address Data Status
Bus Interface and Control
Write Read Transfer Inc/Dec
Power-on Recall Wiper Counter Registers (WCR)
Control
Data Registers (DR0–DR3)
VSS
RW0
RL0
RW1
RL1
50kΩ or 100kΩ versions
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. XDCP is a trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2005, 2006, 2007. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
X9269 Ordering Information
PART NUMBER X9269TS24* X9269TS24I* X9269TS24IZ* (Note) X9269TS24Z* (Note) X9269TV24 X9269US24* X9269US24I* X9269US24IZ* (Note) X9269US24Z* (Note) X9269UV24* X9269UV24I X9269TS24-2.7* X9269TS24I-2.7* X9269TS24IZ-2.7* (Note) X9269TS24Z-2.7* (Note) X9269TV24I-2.7 X9269TV24IZ-2.7* (Note) X9269US24-2.7* X9269US24I-2.7* X9269US24IZ-2.7* (Note) X9269US24Z-2.7* (Note) X9269UV24-2.7* X9269UV24I-2.7* X9269UV24IZ-2.7* PART MARKING X9269TS X9269TS I X9269TS ZI X9269TS Z X9269TV X9269US X9269US I X9269US ZI X9269US Z X9269UV X9269UV I X9269TS F X9269TS G X9269TS ZG X9269TS ZF X9269TV G X9269TV ZG X9269US F X9269US G X9269US ZG X9269US ZF X9269UV F X9269UV G X9269UV ZG 50 2.7 to 5.5 100 50 VCC LIMITS (V) 5 ±10% POTENTIOMETER ORGANIZATION (kΩ) 100 TEMP RANGE (°C) 0 to +70 PACKAGE 24 Ld SOIC (300 mil) PKG. DWG. # M24.3 M24.3 M24.3 M24.3 MDP0044 M24.3 M24.3 M24.3 M24.3 MDP0044 MDP0044 M24.3 M24.3 M24.3 M24.3 MDP0044 MDP0044 M24.3 M24.3 M24.3 M24.3 MDP0044 MDP0044 MDP0044
-40 to +85 24 Ld SOIC (300 mil) -40 to +85 24 Ld SOIC (300 mil) (Pb-free) 0 to +70 0 to +70 0 to +70 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm) 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil) -40 to +85 24 Ld SOIC (300 mil) (Pb-free) 0 to +70 0 to +70 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm)
-40 to +85 24 Ld TSSOP (4.4mm) 0 to +70 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil) -40 to +85 24 Ld SOIC (300 mil) (Pb-free) 0 to +70 24 Ld SOIC (300 mil) (Pb-free)
-40 to +85 24 Ld TSSOP (4.4mm) -40 to +85 24 Ld TSSOP (4.4mm) (Pb-free) 0 to +70 24 Ld SOIC (300 mil)
-40 to +85 24 Ld SOIC (300 mil) -40 to +85 24 Ld SOIC (300 mil) (Pb-free) 0 to +70 0 to +70 24 Ld SOIC (300 mil) (Pb-free) 24 Ld TSSOP (4.4mm)
-40 to +85 24 Ld TSSOP (4.4mm) -40 to +85 24 Ld TSSOP (4.4mm)
*Add "T1" suffix for tape and reel. NOTE: Intersil Pb-free plus anneal products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
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FN8173.4 April 17, 2007
X9269
DETAILED FUNCTIONAL DIAGRAM
RH0 RL0 RW0
VCC
Power-on Recall R0 R1 Wiper Counter Register (WCR)
Pot 0
SCL SDA A3 A2 A1 A0 WP INTERFACE AND CONTROL CIRCUITRY
.