Document
Product Description
Sirenza Microdevices’ XD010-04S-D4F 12W power module is a robust broadband 2-stage Class A/AB amplifier, suitable for use as a power amplifier driver or output stage. The power transistors are fabricated using Sirenza's latest, high performance LDMOS process. It is a drop-in, notune, solution for high power applications requiring high efficiency, excellent linearity, and unit-to-unit repeatability. Internal bias current compensation ensures stable performance over a wide temperature range. It is internally matched to 50 ohms.
XD010-04S-D4F XD010-04S-D4FY
Pb
& Green Package
RoHS Compliant
350-600 MHz Class AB 12W Power Amplifier Module
Functional Block Diagram
Stage 1 Stage 2
Product Features
Bias Network
Temperature Compensation
1
2
3
4
• • • • • • • • • • • • •
Available in RoHS compliant packaging 50 W RF impedance 12W Output P1dB Single Supply Operation : Nominally 28V High Gain: 32 dB at 450 MHz High Efficiency: 30% at 450 MHz Robust 8000V ESD (HBM), Class 3B XeMOS II LDMOS FETS Temperature Compensation
RF in
VD1
VD2 Case Flange = Ground
RF out
Applications
DTV Public Service Wireless Infrastructure Military Communications
Unit MHz W dB dB dB % dBc nS Deg MHz ºC/W ºC/W Min. 350 30 10 26 350 Typ. 12 32 1.0 15 30 -32 2.5 0.5 11 4 Max. 600 2.0 -28 600
Key Specifications
Symbol Frequency P1dB Gain Gain Flatness IRL Efficiency Linearity Delay Phase Linearity Frequency RTH, j-l RTH, j-2 Parameter Frequency of Operation
Output Power at 1dB Compression, 450MHz Gain at 10W Output Power, 450MHz Peak to Peak Gain Variation, 350 - 600MHz Input Return Loss 1W Output Power, 350 - 600MHz Drain Efficiency at 10W CW, 350-600MHz 3rd Order IMD at 10W PEP (Two Tone), 450MHz & 451MHz Signal Delay from Pin 1 to Pin 4 Deviation from Linear Phase (Peak to Peak) Frequency of Operation Thermal Resistance Stage 1 (Junction-to-Case) Thermal Resistance Stage 2 (Junction-to-Case)
Test Conditions Zin = Zout = 50Ω, VDD = 28.0V, IDQ1 = 230 mA, IDQ2 =150 mA, TFlange = 25ºC
1625-1675The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or omissions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any thrid party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2003 Sirenza Microdevices, Inc. All worldwide rights reserved.
303 S. Technology Court, Broomfield, CO 80021
Phone: (800) SMI-MMIC 1
http://www.sirenza.com EDS-104259 Rev D
XD010-04S-D4F 350-600 MHz 12W Power Amp Module
Quality Specifications
Parameter ESD Rating MTTF Human Body Model, JEDEC Document - JESD22-A114-B 85o C Leadframe, 200 C Channel
o
Unit V Hours
Typical 8000 1.2 X 106
Pin Description
Pin # 1 2 3 4 Flange Function RF Input VD1 VD2 RF Output Gnd Description Module RF input. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. This is the drain voltage for the first stage. Nominally +28Vdc This is the drain voltage for the 2nd stage of the amplifier module. The 2nd stage gate bias is temperature compensated to maintain constant quiscent drain current over the operating temperature range. See Note 1. Module RF output. This pin is internally connected to DC ground. Do not apply DC voltages to the RF leads. Care must be taken to protect against video transients that may damage the active devices. Exposed area on the bottom side of the package needs to be mechanically attached to the ground plane of the board for optimum thermal and RF performance. See mounting instructions in application note AN-060 on Sirenza’s web site.
Simplified Device Schematic
2 VD1
Temperature
3 VD2
Bias Network RFin 1 Q1
Compensation
Q2
RFout 4
Case Flange = Ground
Absolute Maximum Ratings
Parameters 1st Stage Bias Voltage (VD1 ) 2nd Stage Bias Voltage (VD2) RF Input Power Load Impedance for Continuous Operation Without Damage Output Device Channel Temperature Operating Temperature Range Storage Temperature Range Value 35 35 +20 5:1 +200 -20 to +90 -40 to +100 Unit V V dBm VSWR ºC ºC ºC
Note 1: The internally generated gate voltage is thermally compensated to maintain constant quiescent current over the temperature range listed in the data sheet. No compensation is provided for gain changes with temperature. This can only be accomplished with AGC external to the module. Note 2: Internal RF decoupling is included on all bias leads. No additional bypass elements are required, however some applications may require energy storage on the drain leads to accommodate time-varying waveforms. No.