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SDM-09120Y Dataheets PDF



Part Number SDM-09120Y
Manufacturers Sirenza Microdevices
Logo Sirenza Microdevices
Description Class AB 130W Power Amplifier Module
Datasheet SDM-09120Y DatasheetSDM-09120Y Datasheet (PDF)

Product Description Sirenza Microdevices’ SDM-09120 130W power module is a robust impedance matched, single-stage, push-pull Class AB amplifier module suitable for use as a power amplifier driver or output stage. The power transistors are fabricated using Sirenza's latest, high performance LDMOS process. It is a drop-in, no-tune solution for high power applications requiring high efficiency, excellent linearity, and unit-tounit repeatability. It is internally matched to 50 ohms. SDM-09120 SDM-0.

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Product Description Sirenza Microdevices’ SDM-09120 130W power module is a robust impedance matched, single-stage, push-pull Class AB amplifier module suitable for use as a power amplifier driver or output stage. The power transistors are fabricated using Sirenza's latest, high performance LDMOS process. It is a drop-in, no-tune solution for high power applications requiring high efficiency, excellent linearity, and unit-tounit repeatability. It is internally matched to 50 ohms. SDM-09120 SDM-09120Y Pb & Green Package RoHS Compliant 925-960 MHz Class AB 130W Power Amplifier Module Functional Block Diagram Vgs +3V DC to +6 V DC +28V DC 1 Vds1 180 o 0 o Gnd Balun RFin Balun Gnd Product Features RF out Gnd 0 +3V DC to +6 V DC o Gnd 180 o Vgs 2 +28V DC Vds 2 • • • • • • Available in RoHS compliant packaging 50 W RF impedance 130W Output P1dB Single Supply Operation : Nominally 28V High Gain: 15 dB at 942 MHz High Efficiency: 42% at 942 MHz Case Flange = Ground Applications Key Specifications Symbol Frequency P1dB Gain Gain Flatness IRL IMD IMD Variation Efficiency Delay Parameter Frequency of Operation Output Power at 1dB Compression, 943 MHz 120W PEP Output Power, 942MHz and 943MHz • • • • Base Station PA driver Repeater CDMA GSM / EDGE Units MHz W dB dB dB dBc dB % % nS Deg Min. 925 120 14 32 Typ. 130 15 0.3 -14 -28 1.0 33 42 4.0 0.7 Max. 960 0.5 -12 -26 - Peak-to-Peak Gain Variation, 120W PEP, 925 - 960MHz Input Return Loss, 120W PEP Output Power, 925 - 960MHz 3rd Order Product. 120W PEP Output, 942MHz and 943MHz 120W PEP Output, Change in Spacing 100KHz - 25MHz Drain Efficiency, 120W PEP Output, 942MHz and 943MHz Drain Efficiency, 120W CW Output, 943MHz Signal Delay from Pin 3 to Pin 8 Phase Linearity Deviation from Linear Phase (Peak-to-Peak) T TFlange = 25ºC Test Conditions Zin = Zout = 50Ω, VDD = 28.0V, IDQ1 = IDQ2 =500mA Quality Specifications Parameter ESD Rating MTTF Description Human Body Model 200oC Channel Unit Volts Hours Typical 2000 1.2 X 106 The information provided herein is believed to be reliable at press time. Sirenza Microdevices assumes no responsibility for inaccuracies or ommisions. Sirenza Microdevices assumes no responsibility for the use of this information, and all such information shall be entirely at the user’s own risk. Prices and specifications are subject to change without notice. No patent rights or licenses to any of the circuits described herein are implied or granted to any third party. Sirenza Microdevices does not authorize or warrant any Sirenza Microdevices product for use in life-support devices and/or systems. Copyright 2005 Sirenza Microdevices, Inc. All worldwide rights reserved. 303 S. Technology Court, Broomfield, CO 80021 Phone: (800) SMI-MMIC 1 http://www.sirenza.com EDS-103478 Rev E SDM-09120 925-960 MHz 130W Power Amp Module Pin Description Pin # 1 2,4,7,9 3 5 6 8 10 Flange Function VGS1 Ground RF Input VGS2 VD2 RF Output VD1 Ground Module Topside ground. Internally DC blocked LDMOS FET Q3 and Q4 gate bias. VGSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4 LDMOS FET Q3 and Q4 drain bias. See Note 1. Internally DC blocked LDMOS FET Q1 and Q2 drain bias. See Note 1. Baseplate provides electrical ground and a thermal transfer path for the device. Proper mounting assures optimal performance and the highest reliability. See Sirenza applications note AN-054 Detailed Installation Instructions for Power Modules. Description LDMOS FET Q1 and Q2 gate bias. VGSTH 3.0 to 5.0 VDC. See Notes 2, 3 and 4 Simplified Device Schematic Q1 1 2 3 +3V DC to +6 V DC +28V DC 10 9 Q2 180 o Note 1: Internal RF decoupling is included on all bias leads. No additional bypass elements are required, however some applications may require energy storage on the VD leads to accommodate modulated signals. Note 2: Gate voltage must be applied to VGS leads simultaneously with or after application of drain voltage to prevent potentially destructive oscillations. Bias voltages should never be applied to a module unless it is properly terminated on both input and output. Note 3: The required VGS corresponding to a specific IDQ will vary from module to module and may differ between VGS1 and VGS2 on the same module by as much as ±0.10 volts due to the normal die-to-die variation in threshold voltage for LDMOS transistors. Unit V dBm VSWR V ºC ºC ºC 0 o Balun Balun 8 Q3 0 o 180 o 4 Q4 7 +3V DC to +6 V DC +28V DC 5 6 Absolute Maximum Ratings Parameters Drain Voltage (VDD) RF Input Power Load Impedance for Continuous Operation Without Damage Control (Gate) Voltage, VDD = 0 VDC Output Device Channel Temperature Operating Temperature Range Storage Temperature Range Value 35 +43 5:1 15 +200 -20 to +90 -40 to +100 Note 4: The threshold voltage (VGSTH) of LDMOS transistors varies with device temperature. External temperature compensation may be required. See Sirenza application notes AN-067 LDMOS Bias Temperature Compensation. Note 5: This module was designed to h.


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