SY89874U
2.5GHz, Any Differential, In-to-LVPECL, Programmable Clock Divider/Fanout Buffer
with Internal Termination
General Description
This low-skew, low-jitter device is capable of accepting a high-speed (e.g., 622MHz or higher) CML, LVPECL, LVDS or HSTL clock input signal and dividing down the frequency using a programmable divider ratio to create a freq...