Micrel, Inc.
Precision Edge®
ULTRA PRECISION DUAL 2:1 CML
Precision ESdY5g8e0®25U
MUX WITH INTERNAL I/O TERMINATION
SY58025U
FEATURES
Two independent differential 2:1 multiplexers Guaranteed AC performance over temperature and
voltage:
• DC-to >10.7Gbps data rate throughput • <290ps IN-to-Out tpd • <70ps tr / tf times Unique, patent-pending input isolation design minimizes crosstalk Ultra-low jitter design: • <1psRMS random jitter • <10psPP deterministic jitter • <10psPP total jitter (clock) • <0.7psRMS crosstalk-induced jitter Unique, patent-pending 50ý input termination and VT pin accepts DC-coupled and AC-coupled inputs (CML, LVDS, PECL) Typical 400mV CML output swing (RL = 50ý) Internal 50ý input termination Power supply 2.5V ±5% or 3.3V ±10% –40°C to +85°C temperature range Available in 32-pin (5mm ∞ 5mm) MLF® package
APPLICATIONS
Data communication systems All SONET OC3-OC-768 applications All Fibre Channel applications All GigE applications
FUNCTIONAL BLOCK DIAGRAM
DESCRIPTION
Precision Edge®
The SY58025U features two ultra-fast, low jitter 2:1 differential muxes with a guaranteed maximum data or clock throughput of 10.7Gbps or 7GHz, respectively.
The SY58025U differential inputs include a unique, internal termination design that allows access to the termination network through a VT pin. The device easily interfaces to different logic standards, both AC- and DCcoupled, without external resistor-bias and termination networks. The result is a clean, stub-free, low jitter interface solution. The differential CML output is optimized for 50ý environments with internal 50ý source termination and a 400mV output swing.
The SY58025U operates from a 2.5V or 3.3V supply and is guaranteed over the full industrial temperature range (–40°C to +85°C). The SY58025U is part of Micrel’s Precision Edge® product family.
All support documentation can be found on Micrel’s web site at www.micrel.com.
INA0 50Ω
VTA0 50Ω
/INA0
VREF-ACA0
INA1 50Ω
VTA1 50Ω
/INA1
0 MUX A
1S
QA /QA
INB0 50Ω
VTB0 50Ω
/INB0
VREF-ACB0
INB1 50Ω
VTB1 50Ω
/INB1
VREF-ACA1
VREF-ACB1
SELA (TTL/CMOS)
SELB (TTL/CMOS)
United States Patent No. RE44,134 AnyGate and Precision Edge are registered trademarks of Micrel, Inc.
MicroLeadFrame and MLF are registered trademarks of Amkor Technology, Inc.
M9999-082707
[email protected] or (408) 955-1690
1
0 MUX B
1S
QB /QB
Rev.: D Amendment: /0 Issue Date: August 2007
Micrel, Inc.
Precision Edge® SY58025U
PACKAGE/ORDERING INFORMATION
INA1 VREF-ACA1 VTA1 INA1 /INA0 VREF-ACA0 VTA0 INA0
INB0
VTB0 VREF-ACB0
/INB0 INB1 VTB1 VREF-ACB1 /INB1
32 31 30 29 28 27 26 25 1 24
2 23 3 22 4 21 5 20 6 19 7 18
8 17 9 10 11 12 13 14 15 16
GND
VCC QA
/QA VCC NC SELA VCC
GND VCC /QB
QB VCC
NC SELB VCC
32-Pin MLF® (MLF-32)
Ordering Information(1)
Part Number SY58025UMI SY58025UMITR(2) SY58025UMG(3)
Package Type
MLF-32
MLF-32 MLF-32
SY58025UMGTR(2, 3) MLF-32
Operating Range
Industrial Industrial Industrial
Industrial
Package Marking
SY58025U
SY58025U
SY58025Uwith Pb-Free bar-line indicator
SY58025U with Pb-Free bar-line indicator
Lead Finish
Sn-Pb
Sn-Pb
Pb-Free NiPdAu
Pb-Free NiPdAu
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25°C, DC electricals only. 2. Tape and Reel. 3. Pb-Free package recommended for new designs.
PIN DESCRIPTION
Pin Number 25, 28, 29, 32, 1, 4, 5, 8
26, 30, 2, 6
18, 15
27, 31, 3, 7
10, 13, 16, 17, 20, 23
22, 21, 12, 11 9, 24 14, 19
Pin Name INA0, /INA0, INA1, /INA1, INB0, /INB0, INB1, /INB1
VTA0 , VTA1, VTB0, VTB1
SELA, SELB
VREF-ACA0, VREF-ACA1, VREF-ACB0, VREF-ACB1
VCC
Pin Function
Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept AC- or DC-coupled differential signals as small as 100mV. Each pin of a pair internally terminates to a VT pin through 50ý. Note that these inputs will default to an indeterminate state if left open. Unused differential input pairs can be terminated by connecting one input to VCC and the complementary input to GND through a 1ký resistor. The VT pin is to be left open in this configuration. Please refer to the “Input Interface Applications” section for more details.
Input Termination Center-Tap: Each side of the differential input pair, terminates to a VT pin. Each VT pin provides a center-tap to a termination network for maximum interface flexibility. See “Input Interface Applications” section for more details.
Bank A, Bank B Input Channel Select (TTL/CMOS): These TTL/CMOS-compatible inputs select the inputs to the multiplexers. These inputs are internally connected to a 25ký pull-up resistor and will default to a logic HIGH state if left open. Input switching threshold is VCC/2.
Reference Output Voltage: These outputs bias to VCC –1.2V. Connect to the VT pin when AC-coupling the data inputs. Bypass with 0.01µF low ESR capacitor to VCC. Maximum current s.