SY100S321

Micrel, Inc. LOW-POWER 9-BIT INVERTER SY100S321 SY100S321 FEATURES DESCRIPTION s Max. propagation delay of 700ps s IEE min. of –55mA s Extended supply voltage option: VEE = –4.2V to –5.5V s Voltage and temperature compensation for improved noise immunity s 70% faster than Fairchild 300K at lower power s Internal 75kΩ input pull-down resistors s Function and pinout compatible with Fairchild F100K s Available in 28-pin PLCC package The SY100S321 is a monolithic 9-bit inverter. The device contains nine inverting buffer gates with single input and output. BLOCK DIAGRAM D1 D2 D3 D4 D5 D6 D7 D8 D9 O1 O2 O3 O4 O5 O6 O7 O8 O9 PIN NAMES Pin D1 – D9 Q1 – Q9 VEES VCCA Function Data Inputs Data Outputs VEE Substrate VCCO for ECL Outputs M9999-042307 [email protected] or (408) 955-1690 1 Rev.: I Amendment: /0 Issue Date: April 2007 Micrel, Inc. SY100S321 PACKAGE/ORDERING INFORMATION D5 D4 VCCA VEES O4 O5 O6 Ordering Information D6 D7 VEE VEES VCCA D8 D9 11 10 9 8 7 6 5 12 13 14 Top View 15 PLCC J28-1 16 17 18 4 3 2 1 28 27 26 19 20 21 22 23 24 25 O7 O8 VCCA VCC VCC O9 O1 D1 D2 D3 VEES VCCA O3 O2 28-Pin PLCC (J28-1) Part Number SY100S321JC SY100S321JCTR(1) SY100S321JZ(2) Package Type J28-1 J28-1 J28-1 SY100S321JZTR(1, 2) J28-1 Operating Range Commercial Commercial Commercial Commercial Package Marking SY100S321JC SY100S321JC SY100S321JZ with Pb-Free bar-line indicator SY100S321JZ with Pb-Free bar-line indicator Lead Finish Sn-Pb Sn-Pb Matte-Sn Matt...