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T83C5102 Dataheets PDF



Part Number T83C5102
Manufacturers ATMEL Corporation
Logo ATMEL Corporation
Description (T83C5101x) 8-bit Low Pin Count Microcontrollers
Datasheet T83C5102 DatasheetT83C5102 Datasheet (PDF)

Features • 80C51 Code Compatible – 8051 Instruction Compatible – 16 I/O + 2 Outputs in 24 Pin Packages 16 I/O + 6 Outputs in 28 Pin Packages – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM Program Memory – 8 KB ROM T83C5102 – 16 KB ROM T83C5101 – 16 KB EPROM/OTP T87C5101 High-speed Architecture 40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range: – 40 MHz with a 40 MHz Crystal In Std. Mode – 40 MHz with a 20 MHz Crystal In X2 Mode 66 MHz from 4.5 to 5.5V, Commercial Temp.

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Features • 80C51 Code Compatible – 8051 Instruction Compatible – 16 I/O + 2 Outputs in 24 Pin Packages 16 I/O + 6 Outputs in 28 Pin Packages – Three 16-bit Timer/Counters – 256 Bytes Scratchpad RAM Program Memory – 8 KB ROM T83C5102 – 16 KB ROM T83C5101 – 16 KB EPROM/OTP T87C5101 High-speed Architecture 40 MHz from 2.7 to 5.5V, Commercial or Industrial Temperature Range: – 40 MHz with a 40 MHz Crystal In Std. Mode – 40 MHz with a 20 MHz Crystal In X2 Mode 66 MHz from 4.5 to 5.5V, Commercial Temperature Range – 40 MHz with a 40 MHz Crystal in Std. Mode – 66 MHz with a 33 MHz Crystal in X2 Mode Dual Data Pointer On-chip eXpanded RAM (XRAM) (256 bytes) Programmable Clock Out and Up/Down Timer/Counter 2 Asynchronous Port Reset Interrupt Structure with – 6 Interrupt Sources, – 4-Level Priority Interrupt System Full-duplex Enhanced UART – Framing Error Detection – Automatic Address Recognition Low EMI (no ALE) www.DataSheet4U.com Power Control Modes – Idle Mode – Power-down Mode Packages: SO24, DIL24, SSOP24, SO28 • • • • • • • • • • • • • 8-bit Low Pin Count Microcontrollers T83C5101 T87C5101 T83C5102 Description The T8xC5101/02 family is a high performance CMOS ROM, OTP, EPROM derivative of the 80C51 CMOS single chip 8-bit microcontroller. The T8xC5101/02 family is a low pin count device where only Port 1, port 3 and 2/6 bits of a new port 4 are outputted. This prevents any external access, like external program memory access (fetch, MOVC) or external data memory (MOVX). The T8xC5101/02 family retains all features of the 80C51 with extended capacity 8 KB ROM (5102), 16 KB ROM (5101)/16 KB EPROM/OTP (5101), 256 bytes of internal RAM, a 6-source, 4-level interrupt system, an on-chip oscillator and three timer/counters. In addition, the T8xC5101/02 family has an XRAM of 256 bytes, the X2 feature, a more versatile serial channel that facilitates multiprocessor communication (EUART), a dual data pointer and an improved timer 2. The fully static design of the T8xC5101/02 family allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The T8xC5101/02 family has 2 software-selectable modes of reduced activity for further reduction in power consumption. In idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In power-down mode the RAM is saved and all other functions are inoperative. Rev. 4233G–8051–03/03 1 Block Diagram T2EX (1) XRAM 256x8 RxD TxD Vcc Vss (2) (2) XTAL1 XTAL2 PROG TEST (3) (3) CPU VPP Timer 0 Timer 1 INT Ctrl Parallel I/O Ports Port 1 Port 4 Port 3 C51 CORE (1) EUART RAM 256x8 ROM /EPROM 16Kx8 Timer2 IB-bus (2) (2) T0 RESET T1 (2) (2) P1 P4 INT0 INT1 P3 (1): Alternate function of Port 1 (2): Alternate function of Port 3 (3): Multiplexed function of Port 4. 2 T8xC5101/02 4233G–8051–03/03 T2 T8xC5101/02 SFR Mapping The Special Function Registers (SFRs) of the T8xC5101/02 fall into the following categories: • • • • • • • C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1 I/O port registers: P1, P3, P4 Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H Serial I/O port registers: SADDR, SADEN, SBUF, SCON Power and clock control registers: PCON Interrupt system registers: IE, IP, IPH Others: AUXR, CKCON No write must be made to reserved areas. Reading a reserved area will give indeterminate results. 3 4233G–8051–03/03 Table 1. All SFRs With Their Address and Rest Values Bit addressable 0/8 1/9 2/A 3/B Non Bit addressable 4/C 5/D 6/E 7/F F8h F0h B 0000 0000 FFh F7h E8h E0h ACC 0000 0000 EFh E7h D8h D0h PSW 0000 0000 T2CON 0000 0000 P4 XX11 1111 B8h IP XX00 000 B0h P3 1111 1111 A8h IE 0X00 0000 A0h SADDR 0000 0000 AUXR1 XXXX0XX0 98h SCON 0000 0000 90h P1 1111 1111 88h TCON 0000 0000 80h TMOD 0000 0000 SP 0000 0111 0/8 1/9 DFh D7h C8h T2MOD XXXX XX00 RCAP2L 0000 0000 RCAP2H 0000 0000 TL2 0000 0000 TH2 0000 0000 CFh C0h C7h SADEN 0000 0000 IPH XX00 0000 BFh B7h AFh A7h SBUF XXXX XXXX 9Fh 97h TL0 0000 0000 DPL 0000 0000 2/A TL1 0000 0000 DPH 0000 0000 3/B TH0 0000 0000 TH1 0000 0000 AUXR XXXXXX00 CKCON XXXX XXX0 PCON 00X1 0000 8Fh 87h 4/C 5/D 6/E 7/F Reserved 4 T8xC5101/02 4233G–8051–03/03 T8xC5101/02 T8xC5101/02 Pin Configuration P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1 P3.0 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 Vcc P3.5/T1 P3.6 P3.7 P1.7 P1.6 P1.5 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 P3.4/T0 P3.3/INT1 P3.2/INT0 P3.1 P3.0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 Vcc P4.2 P3.5/T1 P3.6 P3.7 P1.7 P1.6 P4.5 P1.5 P1.4 P1.3 P1.2 P1.1/T2EX P1.0/T2 VPP P4.0/Prog P4.1/Test RST XTAL2 XTAL1 Vss DIL24 SO24 SSOP24* 20 19 18 17 16 15 14 13 VPP P4.3 P4.0/Prog P4.1/Test RST XTAL2 XTAL1 P4.4 Vss SO28* 22 21 20 19 18 17 16 15 * Check for availability * Check for availability Pin Number 28 pins 14 28 15-20 22-23 Mnemonic VSS VCC P1.0-P1.7 24 pins 12 24 13-20 Type I I I/O Name and Function Ground.


T83C5101 T83C5102 T87C5101


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