M13L128168A

ESMT Revision History Revision 1.3 -Revise operation voltage. (page 5) Revision 1.2 -Changed tWTR from 1 tCK to 2 tCK. Revision 1.1 -Changed absolute max. voltage (VIN, VOUT ,VDD ,VDDQ) from 3.6V to 4.0V Parameter Voltage on any pin relative to VSS Voltage on VDD supply relative to VSS Voltage on VDDQ supply relative to VSS Symbol VIN, VOUT VDD VDDQ Value -0.5 ~ 4.0 -1.0 ~ 4.0 -0.5 ~ 4.0 Unit V V V M13L128168A -Changed operating VDD from 3.135V~3.6V to 3.135V~3.83V -Updated DC current specification Revision 1.0 (21 Oct. 2002) -No “preliminary” on title. -Added M13L128168A-3.6T Spec. -Changed VDDQ from 2.5V ± 5% to 2.375V ~ 2.8V Revision 0.4 (26 Sep. 2002) -Changed VDD from 3.3V ± 5% to 3.135V ~ 3.6V -Changed operating temperature from 70 °C to 65 °C Revision 0.3 (11 Jul. 2002) -Added DC Current Spec Revision 0.2 (29 May. 2002) -Independent of M13S128168A Revision 0.1 (3 May. 2002) -Original www.DataSheet4U.com Elite Semiconductor Memory Technology Inc. Publication Date : Jun. 2003 Revision : 1.3 1/48 ESMT DDR SDRAM Features z z z z z z z z z z z z z z z z z z z z M13L128168A 2M x 16 Bit x 4 Banks Double Data Rate SDRAM JEDEC Standard Internal pipelined double-data-rate architecture, two data access per clock cycle Bi-directional data strobe(DQS) On-chip DLL Differential clock inputs (CLK and CLK ) DLL aligns DQ and DQS transition with CLK transition Quad bank operation CAS Latency : 2, 3 Burst Type : Sequential and Interleave Burst Length : 2, 4, 8 All inputs except da...