MC100EPT622

3.3 V LVTTL/LVCMOS to LVPECL Translator MC100EPT622 Description The MC100EPT622 is a 10−Bit LVTTL/LVCMOS to LVPECL translator. Because LVPECL (Positive ECL) levels are used only +3.3 V and ground are required. The device has an OR−ed enable input which can accept either LVPECL (ENPECL) or TTL/LVCMOS inputs (ENTTL). If the inputs are left open, they will default to the enable state. The device design has been optimized for low channel−to−channel skew. Features 450 ps Typical Propagation Delay Maximum Frequency > 1.5 GHz Typical PECL Mode Operating Range: VCC = 3.0 V to 3.8 V with VEE = 0 V PNP LVTTL Inputs for Minimal Loading Q Output Will Default HIGH with Inputs Open The 100 Series Contains Temperature Compensation These Devices are Pb−Free, Halogen Free and are RoHS Compliant www.onsemi.com MARKING DIAGRAMS* LQFP−32 FA SUFFIX CASE 561AB MC100 EPT622 AWLYYWWG 32 1 1 32 QFN32 MN SUFFIX CASE 488AM 1 MC100 EPT622 AWLYYWWG G A WL YY WW G or G = Assembly Location = Wafer Lot = Year = Work Week = Pb−Free Package (Note: Microdot may be in either location) *For additional marking information, refer to Application Note AND8002/D. Table 1. TRUTH TABLE ENPECL ENTTL D Q H X H H H X L L X H H H X H L L L L X L ORDERING INFORMATION See detailed ordering and shipping information in the package dimensions section on page 6 of this data sheet. © Semiconductor Components Industries, LLC, 2011 1 March, 2021 − Rev. 7 Publication Order Numbe...