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STD100N3LF3 STU100N3LF3
N-channel 30V - 0.0045Ω - 80A - DPAK - IPAK Planar STripFET™ II Power MOSFET
General features
Type STD100N3LF3 STU100N3LF3 VDSSS 30 V 30 V RDS(on) ID Pw
3 1
2 1
<0.0055 Ω 80 A(1) 110 W <0.0055 Ω 80 A(1) 110 W
3
1. Current limited by package ■ ■
100% avalanche tested Logic level threshold
DPAK
IPAK
Description
This Power MOSFET is the latest refinement of STMicroelectronics unique “Single Feature Size™” strip-based process. The resulting transistor shows extremely high packing density for low on-resistance, rugged avalanche characteristics, low gate charge and less critical alignment steps therefore a remarkable manufacturing reproducibility. This new improved device has been specifically designed for Automotive application and DC-DC converters.
Internal schematic diagram
Applications
■
Switching application
Order codes
Part number STD100N3LF3 STU100N3LF3 Marking 100N3LF3 100N3LF3 Package DPAK IPAK Packaging Tape & reel Tube
February 2007
Rev 1
1/15
www.st.com 15
Contents
STD100N3LF3 - STU100N3LF3
Contents
1 2 Electrical ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2.1 Electrical characteristics (curves) ............................ 6
3 4 5 6
Test circuit
................................................ 9
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Packaging mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
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STD100N3LF3 - STU100N3LF3
Electrical ratings
1
Electrical ratings
Table 1.
Symbol VDS ID
(1)
Absolute maximum ratings
Parameter Drain-source voltage (VGS = 0) Drain current (continuous) at TC = 25°C Drain current (continuous) at TC=100°C Drain current (pulsed) Total dissipation at TC = 25°C Derating factor Value 30 80 70 320 110 0.73 3.9 -55 to 175 Max. operating junction temperature Unit V A A A W W/°C V/ns °C
ID IDM (2) PTOT
dv/dt (3) Peak diode recovery voltage slope Tstg TJ Storage temperature
1. Current limited by package. 2. Pulse width limited by safe operating area 3. ISD ≤80A, di/dt ≤360 A/µs, VDS ≤V(BR)DSS, TJ ≤TJMAX
Table 2.
Symbol RthJC RthJA Tl
Thermal data
Parameter Thermal resistance junction-case Max Thermal resistance junction-ambient Max Maximum lead temperature for soldering purpose Value 1.36 100 275 Unit °C/W °C/W °C
Table 3.
Symbol IAR EAS
Avalanche characteristics
Parameter Not-repetitive avalanche current (pulse width limited by TJ max) Single pulsed avalanche energy (starting TJ = 25°C, ID = IAV, VDD = 24V Value 40 Unit A
500
mJ
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Electrical characteristics
STD100N3LF3 - STU100N3LF3
2
Electrical characteristics
(TCASE=25°C unless otherwise specified) Table 4.
Symbol V(BR)DSS IDSS IGSS VGS(th)
On/off states
Parameter Drain-source breakdown voltage Zero gate voltage drain current (VGS = 0) Gate body leakage current (VDS = 0) Gate threshold voltage Test conditions ID = 250µA, VGS = 0 VDS = Max rating, VDS = Max rating @125°C VGS = ±20V VDS= VGS, ID = 250µA VGS = 10V, ID = 40A VGS = 5V, ID = 20A Static drain-source on resistance VGS = 10 V, ID = 40 A @125°C VGS = 5 V, ID = 20 A @125°C 1 0.0045 0.0055 0.008 0.01 Min. 30 1 10 ±200 Typ. Max. Unit V µA µA nA V Ω Ω Ω Ω
RDS(on)
0.0068 0.0146
Table 5.
Symbol gfs (1) Ciss Coss Crss Qg Qgs Qgd RG
Dynamic
Parameter Forward transconductance Input capacitance Output capacitance Reverse transfer capacitance Total gate charge Gate-source charge Gate-drain charge Test conditions VDS = 10 V, ID = 15A VDS = 25V, f = 1 MHz, VGS = 0 VDD = 24V, ID = 80A VGS = 5V Figure 15 on page 9 f = 1MHz gate DC Bias = 0 Test signal level = 20mV Open drain Min. Typ. 31 2060 728 67 20 7 7.5 27 Max. Unit S pF pF pF nC nC nC Ω
Gate input resistance
1.9
1. Pulsed: pulse duration=300µs, duty cycle 1.5%
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STD100N3LF3 - STU100N3LF3
Electrical characteristics
Table 6.
Symbol td(on) tr td(off) tf
Switching times
Parameter Turn-on delay time Rise time Turn-off delay time Fall time Test conditions VDD= 15V, ID= 40A, RG=4.7Ω, VGS=10V Figure 14 on page 9 Min. Typ. 9 205 31 35 Max. Unit ns ns ns ns
Table 7.
Symbol ISD ISDM(1) VSD(2) trr Qrr IRRM
Source drain diode
Parameter Source-drain current Source-drain current (pulsed) Forward on voltage Reverse recovery time Reverse recovery charge Reverse recovery current ISD = 40A, VGS = 0 ISD = 80A, di/dt = 100A/µs, VDD = 25V, TJ = 150°C Figure 16 on page 9 40 40 2 Test conditions Min Typ. Max 80 320 1.3 Unit A A V ns µC A
1. Pulse width limited by safe operating area 2. Pulsed: pulse duration=300µs, duty cycle 1.5%
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Electrical characteristics
STD100N3LF3 - STU100N3LF3
2.1
Figure 1.
Electrical characteristics (curves)
Safe operating area Figure 2. Thermal impedance
Figure .