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ZL30105

Zarlink Semiconductor

T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer

ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA™ and H.110 Data Sheet Features • Synchr...


Zarlink Semiconductor

ZL30105

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Description
ZL30105 T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA™ and H.110 Data Sheet Features Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock Supports ITU-T G.813 option 1, G.823 for 2048 kbit/s and G.824 for 1544 kbit/s interfaces Supports Telcordia GR-1244-CORE Stratum 3/4/4E Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs Provides a range of clock outputs: 1.544 MHz (DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz, and 19.44 MHz (SDH), and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz, and a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3) Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse Holdover frequency accuracy of 1x10-8 Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications April 2010 Ordering Information ZL30105QDG1 64 pin TQFP* Trays Bake & Drypack * Pb Free Matte Tin -40°C to +85°C Less than 0.6 nspp intrinsic jitter on all output clocks and frame pulses Manual or Automatic hitless reference switching between any combination of valid input reference frequencies Provides Lock, Holdover and selec...




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