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IDT709189L Dataheets PDF



Part Number IDT709189L
Manufacturers IDT
Logo IDT
Description HIGH-SPEED 64K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Datasheet IDT709189L DatasheetIDT709189L Datasheet (PDF)

www.DataSheet4U.com HIGH-SPEED 64K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features x x IDT709189L x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 7.5/9/12ns (max.) Low-power operation – IDT709189L Active: 1.2W (typ.) Standby: 2.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion.

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www.DataSheet4U.com HIGH-SPEED 64K x 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM Features x x IDT709189L x x x x True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access – Commercial: 7.5/9/12ns (max.) Low-power operation – IDT709189L Active: 1.2W (typ.) Standby: 2.5mW (typ.) Flow-Through or Pipelined output mode on either Port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic x x x x Full synchronous operation on both ports – 4ns setup to clock and 0ns hold on all control, data, and address inputs – Data input, address, and control registers – Fast 7.5ns clock to data out in the Pipelined output mode – Self-timed write allows fast cycle time – 12ns cycle time, 83MHz operation in Pipelined output mode TTL- compatible, single 5V (±10%) power supply Industrial temperature range (–40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP) package Functional Block Diagram R/WL OEL CE0L CE1L R/WR OER CE0R CE1R 1 0 0/1 1 0 0/1 FT/PIPEL 0/1 1 0 0 1 0/1 FT/PIPER I/O0L - I/O8L I/O0R - I/O8R I/O Control I/O Control A15L A0L CLKL ADSL CNTENL CNTRSTL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A15R A0R CLKR ADSR CNTENR CNTRSTR 4848 drw 01 JANUARY 2001 1 ©2000 Integrated Device Technology, Inc. DSC-4848/3 IDT709189L High-Speed 64K x 9 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Description The IDT709189 is a high-speed 64K x 9 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT709189 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT’s CMOS high-performance technology, these devices typically operate on only 1.2W of power. Index NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL GND GND ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R Pin Configurations(1,2,3) NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L NC VCC NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 4 72 1 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 NC IDT709189PF PN100-1(4) 100-Pin TQFP Top View(5) 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R NC GND NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER GND NC 4848 drw 02 , NOTES: 1. All VCC pins must be connected to power supply. 2. All GND pins must be connected to ground. 3. Package body is approximately 14mm x 14mm x 1.4mm 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking. GND I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R NC NC 2 6.42 IDT709189L High-Speed 64K x 9 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges Pin Names Left Port CE0L, CE1L R/WL OEL A0L - A15L I/O0L - I/O8L CLK L ADSL CNTENL CNTRSTL FT/PIPEL Right Port CE0R, CE1R R/WR OER A0R - A15R I/O0R - I/O8R CLKR ADSR CNTENR CNTRSTR FT/PIPER VCC GND Names Chip Enables Read/Write Enable Output Enable Address Data Input/Output Clock Address Strobe Counter Enable Counter Reset Flow-Through/Pipeline Power Ground 4848 tbl 01 Truth Table I—Read/Write and Enable Control(1,2,3) OE X X X L H CLK ↑ ↑ ↑ ↑ X CE0 H X L L L CE1 X L H H H R/W X X L H X I/O0-8 High-Z High-Z DATAIN DATAOUT High-Z Deselected—Power Down Deselected —Power Down Write Read Outputs Disabled 4848 tbl 02 Mode NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. Truth Table II—Address Counter Control(1,2,6) Address X An An X Previous Address X X Ap Ap Addr Used 0 An Ap Ap + 1 CLK(3) ↑ ↑ ↑ ↑ ADS X L(4) H H CNTEN X X H L (5) CNTRST L H H H I/O(3) DI/O(0) DI/O(n) DI/O(n) DI/O(n+1) Mode Counter Reset to Address 0 External Address Utilized External Address Blocked —Counter Disabled Counter Enable—Internal Address Generation 4848 tbl 03 NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0 and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0 .


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