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ST7162
UNIVERSAL PROGRAMMABLE DUAL PLL
PRODUCT PREVIEW
TWO INDEPENDENT PLL WITH 16 BITS PROGRAMMABLE DIVIDERS FROM 13 TO 65535 FOR TRANSMIT AND RECEIVE LOOPS ON CHIP REFERENCE OSCILLATOR COMMON FOR THE TWO LOOPS UP TO 16MHz WITH EXTERNAL CRYSTAL TWO INDEPENDENT PROGRAMMABLE REFERENCE COUNTERS: - 12 bits programmable counter from 13 to 4095 followed by selectable dividers by 1, 4 and 25 - 14 bits auxiliary programmable counter from 13 to 16383 A MCU CLOCK DERIVED FROM REFERENCE OSCILLATOR WITH A SELECTABLE DIVISION FACTOR OF 3 OR 4 TWO INDEPENDENT PFD (PHASE FREQUENCY DISCRIMINATOR) WITH 3 STATE OUTPUTS LOCK DETECT SIGNAL OUTPUT FOR THE TRANSMIT LOOP 3 & 4 WIRES SELECTABLE MCU SERIAL INTERFACE, FOR SIMULTANEOUS PROGRAMMING OF 2 COUNTERS STAND-BY MODE MAIN CHARACTERISTICS High input sensitivity: 200mVpkpk @ 60MHz Low consumption: 3.5mA @ 3V for the two loops Power supply voltage: 3V to 5V Operating temperature range: –25°C to +70°C
DIP16 ORDERING NUMBER: ST7162N
SO16 ORDERING NUMBER: ST7162D
PIN CONNECTION (Top view)
DESCRIPTION The ST7162 is a dual frequency synthesizer in High Speed CMOS technology for radio applications with a frequency up to 60MHz. The low power consumption and high flexibility make it well suitable for cordless CT0 applications in various countries.
July 1993
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This is advanced information on a new product now in development or undergoing evaluation. Details are subject to change without notice.
ST7162
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
Symbol VDD - VSS VIN VOUT IIN, IOUT IDD, ISS Tstg Supply Voltage Input Voltage Output Voltage DC Current per pin DC Current for pin VDD or VSS Storage Temperature Parameter Value – 0.5 to +6 VSS –0.5 to VDD +0.5 VSS –0.5 to VDD +0.5 – 10 to 10 – 30 to 30 – 55 to +125 Unit V V V mA mA °C
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ST7162
PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name CLOCK AUX DATA IN DATA IN ENABLE MCU CLOCK VSS OSC OUT OSC IN FIN RX PD RX Out RX VDD OUT TX FIN TX PD TX LD MCU Interface MCU Interface MCU Interface MCU Interface Scaled down reference frequency for clocking the MCU Negative Power Supply Oscillator Output Oscillator Input Input to the 16 bits Receive Counter Phase detector output of the Receive loop Power saving output bit for the RX loop and FIN RX divided by N1 for testing the RX input sensitivity. Positive power supply Power saving output bit for the TX loop and FIN TX divided by N2 for testing the TX input sensitivity. Input to the 16 bits Transmit counter. Phase detector output of the transmit loop Lock detect output of the transmit loop. Function
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, voltage reference = VSS)
Symbol SUPPLY VDD IDD up Supply Voltage Supply Current 200mVpkpk sinus at input; FIN RX = 36MHz, FIN TX =49MHz; loop in lock condition; fosc = 10.24MHz; no output load 200mVpkpk sinus at input; FIN RX = 36MHz; TX Loop in Power down; fosc = 10.24MHz; no output load Stand-by mode for all counters; OSCIN pin Grounded; MCU interface disabled 3V 5V 3V 5V 3V 5V 3 5.5 3.7 7.7 2.5 5.3 150 300 8 0 < VIN < VDD Input = sinus 200mVpkpk AC coupled 3V 5V 3-5V – 60 – 100 60 100 60 V mA mA mA mA µA µA pF µA µA MHz Parameter Test Condition VDD Min. Typ. Max. Unit
IDDRX
Supply Current
IDD down
Supply Current
TX and RX INPUTS C IN IIN up Fmax Input Capacitance Input Current Input Frequency
OSCILLATOR C IN COUT IIN up Fmax Input Capacitance Output Capacitance Input Current Input Frequency 0 < VIN < VDD DC measured 3V 5V 3-5V – 60 – 100 8 8 60 100 16 pF pF µA µA MHz
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ST7162
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, voltage reference = VSS)
Symbol COUT IOUT HI Parameter Output Capacitance Output Current Source VOUT = 2.7V VOUT = 4.5V Sink VOUT = 0.3V VOUT = 0.5V Three state output VPDTX, VPDRX = 0 or 5V 3V 5V 3V 5V 5V – 200 – 500 200 500 – 50 50 Test Condition VDD Min. Typ. Max. 8 Unit pF µA µA µA µA nA PHASE FREQUENCY DISCRIMINATOR
IOUT LO
Output Current
ILEAK
Leakage Current
MCU INTERFACE INPUTS C IN IIN VIH Input Capacitance Input Current Input Voltage DC measured VIN = VDD or VSS High level ”1” 3-5V 3V 5V VIL Input Voltage Low level ”0” 3V 5V Fmax TW Input Frequency Pulse width Maximum frequency at clock input Clock and Enable inputs 3-5V 3V 5V TSU Set-up Time Data to clock Enable to clock THOLD Hold Time Clock to data 3-5V 3-5V 3V 5V TREC Recovery Time Enable to Clock 3V 5V DIGITAL OUTPUTS: OUTTX, OUTRX, MCUCLOCK, LD CLOAD VOUT IH Output Load Capacitance Output Voltage IOUT = 0, High level ”1” 3V 5V VOUT LO Output Voltage IOUT = 0, Low level ”0” 3V 5V IOUTHI Output Current Source VOUT = 2.7V VOUT = 4.5V Sink VOUT = 0.3V VOUT = 0.5V CLOAD = 25pF 3V 5V 3V 5V 3V 5V TLO Output Fall Time CLOAD = 25pF 3V 5V 4/17 – 200 – 500 200 500 200 100 200 100 2.95 4.95 0.05 0.05 25 pF V V V V µA µA µA µA ns ns ns ns 80 60 100 200 80 40 80 40 – 10 2.3 3.8 0.7 1.2 500 8 10 pF µA V V V V KHz ns ns ns ns ns ns ns ns
IOUTLO
Output Current
THI
Output rise Time
ST7162
Figure 1: Control Unit Block Diagram
Sumary of I.