T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
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XRT86VL3x
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
JULY 2006 REV. 1.2.0
GENERAL DESCRI...
Description
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XRT86VL3x
T1/E1/J1 FRAMER/LIU COMBO - ARCHITECTURE DESCRIPTION
JULY 2006 REV. 1.2.0
GENERAL DESCRIPTION
The XRT86VL3x is a 1.544 Mbit/s or 2.048 Mbit/s DS1/E1/J1 framer and LIU integrated solution featuring R3 technology (Relayless, Reconfigurable, Redundancy) that comes in a 2-channel, 4-channel, or 8-channel package. The physical interface is optimized with internal impedance, and with the patented pad structure, the XRT86VL3x provides protection from power failures and hot swapping. The XRT86VL3x contains an integrated DS1/E1/J1 framer and LIU which provide DS1/E1/J1 framing and error accumulation in accordance with ANSI/ITU_T specifications. Each framer has its own framing synchronizer and transmit-receive slip buffers. The slip buffers can be independently enabled or disabled as required and can be configured to frame to the common DS1/E1/J1 signal formats. Each Framer block contains its own Transmit and Receive T1/E1/J1 Framing function. There are 3 Transmit HDLC controllers per channel which encapsulate contents of the Transmit HDLC buffers into LAPD Message frames. There are 3 Receive HDLC controllers per channel which extract the
payload content of Receive LAPD Message frames from the incoming T1/E1/J1 data stream and write the contents into the Receive HDLC buffers. Each framer also contains a Transmit and Overhead Data Input port, which permits Data Link Terminal Equipment direct access to the outbound T1/E1/J1 frames. Likewise, a Receive Ove...
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