ICS8531-01

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS8531-01 LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-3.3V LVPECL FANOUT BUFFER FEATURES 9 differential 3.3V LVPECL outputs Selectable CLK, nCLK or LVPECL clock inputs CLK, nCLK pair can accept the following differential input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL PCLK, nPCLK supports the following input types: LVPECL, CML, SSTL Maximum output frequency up to 500MHz Translates any single ended input signal (LVCMOS, LVTTL, GTL) to 3.3V LVPECL levels with resistor bias on nCLK input Output skew: 50ps (maximum) Part-to-part skew: 250ps (maximum) Propagation delay: 2ns (maximum) 3.3V operating supply 0°C to 70°C ambient operating temperature Industrial temperature information available upon request GENERAL DESCRIPTION The ICS8531-01 is a low skew, high performance 1-to-9 Differential-to-3.3V LVPECL Fanout Buffer HiPerClockS™ and a member of the HiPerClockS™ family of High Performance Clock Solutions from ICS. The ICS8531-01 has two selectable clock inputs. The CLK, nCLK pair can accept most standard differential input levels. The PCLK, nPCLK pair can accept LVPECL, CML, or SSTL input levels. The clock enable is internally synchronized to eliminate runt pulses on the outputs during asynchronous assertion/deassertion of the clock enable pin. ,&6 Guaranteed output skew and part-to-part skew characteristics make the ICS8531-01 ideal for high performance workstation and server applications. BLOCK DIAGRAM CLK_EN...