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ICS853013 Dataheets PDF



Part Number ICS853013
Manufacturers ICST
Logo ICST
Description LVPECL/ECL FANOUT BUFFER
Datasheet ICS853013 DatasheetICS853013 Datasheet (PDF)

www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS853013 LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER FEATURES • Two differential LVPECL / ECL bank outputs • Two differential LVPECL clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >2GHz (typical) • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input • Output skew: 40ps (maximum) •.

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www.DataSheet4U.com Integrated Circuit Systems, Inc. ICS853013 LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER FEATURES • Two differential LVPECL / ECL bank outputs • Two differential LVPECL clock input pairs • PCLKx, nPCLKx pairs can accept the following differential input levels: LVPECL, LVDS, CML, SSTL • Output frequency: >2GHz (typical) • Translates any single ended input signal to LVPECL levels with resistor bias on nPCLKx input • Output skew: 40ps (maximum) • Part-to-part skew: 250ps (maximum) • Propagation delay: 570ps (maximum) • Additive phase jitter, RMS: 0.03ps (typical) • LVPECL mode operating voltage supply range: VCC = 2.375V to 5.25V • ECL mode operating voltage supply range: VCC = 0V, VEE = -5.25V to -2.375V • -40°C to 85°C ambient operating temperature • Available in both standard and lead-free RoHS-compliant packages GENERAL DESCRIPTION The ICS853013 is a low skew, high performance dual 1-to-3 Differential-to-2.5V/3.3V/5V HiPerClockS™ LVPECL/ECL Fanout Buffer and a member of the HiperclocksTM family of High Performance Clock Solutions from ICS. The ICS853013 operates with a positive or negative power supply at 2.5V, 3.3V, or 5V. Guaranteed output and part-to-par t skew characteristics make the ICS853013 ideal for those clock distribution applications demanding well defined performance and repeatability. IC S BLOCK DIAGRAM PCLKA nPCLKA QA0 nQA0 QA1 nQA1 QA2 nQA2 PIN ASSIGNMENT nQA0 QA0 VCC PCLKA nPCLKA PCLKB nPCLKB VCC nQB0 QB0 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 QA1 nQA1 QA2 nQA2 VCC QB2 nQB2 QB1 nQB1 VEE PCLKB nPCLKB QB0 nQB0 QB1 nQB1 QB2 nQB2 ICS853013 20-Lead, 300-MIL SOIC 7.5mm x 12.8mm x 2.3mm body package M Package Top View 853013AM www.icst.com/products/hiperclocks.html 1 REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS853013 LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER Type Description Differential output pair. LVPECL interface levels. Power supply pins. Pulldown Pullup/ Pulldown Pulldown Pullup/ Pulldown Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Non-inver ting differential LVPECL clock input. Inver ting differential LVPECL clock input. VCC/2 default when left floating. Differential output pair. LVPECL interface levels. Negative supply pin. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. TABLE 1. PIN DESCRIPTIONS Number 1, 2 3, 8, 16 4 5 6 7 9, 10 11 12, 13 14, 15 17, 18 19, 20 Name nQA0, QA0 VCC PCLKA nPCLKA PCLKB nPCLKB nQB0, QB0 VEE nQB1, QB1 nQB2, QB2 nQA2, QA2 nQA1, QA1 Power Input Input Input Input Output Power Output Output Output Output Output NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values. TABLE 2. PIN CHARACTERISTICS Symbol RPULLDOWN RVCC/2 Parameter Input Pulldown Resistor Pullup/Pulldown Resistors Test Conditions Minimum Typical 75 50 Maximum Units kΩ kΩ TABLE 3. CLOCK INPUT FUNCTION TABLE Inputs PCLKA or PCLKB 0 1 0 1 Biased; NOTE 1 Biased; NOTE 1 nPCLKA or nPCLKB 1 0 Biased; NOTE 1 Biased; NOTE 1 0 1 Outputs QA0:QA2, nQA0:nQA2, QB0:QB2 nQB0:nQB2 HIGH LOW HIGH LOW HIGH HIGH LOW LOW HIGH LOW LOW HIGH Input to Output Mode Differential to Differential Differential to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Single Ended to Differential Polarity Non Inver ting Non Inver ting Non Inver ting Non Inver ting Inver ting Inver ting NOTE 1: Please refer to the Application Information, "Wiring the Differential Input to Accept Single Ended Levels". 853013AM www.icst.com/products/hiperclocks.html 2 REV. A OCTOBER 19, 2005 Integrated Circuit Systems, Inc. ICS853013 LOW SKEW, DUAL, 1-TO-3, DIFFERENTIAL-TO2.5V/3.3V/5V LVPECL/ECL FANOUT BUFFER 5.5V (LVPECL mode, VEE = 0) NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage -5.5V (ECL mode, VCC = 0) -0.5V to VCC + 0.5V 0.5V to VEE - 0.5V 50mA 100mA -65°C to 150°C 46.2°C/W (0 lfpm) to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, VCC Negative Supply Voltage, VEE Inputs, VI (LVPECL mode) Inputs, VI (ECL mode) Outputs, IO Continuous Current Surge Current Storage Temperature, TSTG Package Thermal Impedance, θJA (Junction-to-Ambient) Operating Temperature Range, TA -40°C to +85°C TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = 2.375 TO 5.25V; VEE = 0V Symbol VCC IEE Parameter Power Supply Voltage Power Supply Current Test Conditi.


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