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K4M56163PG Dataheets PDF



Part Number K4M56163PG
Manufacturers Samsung semiconductor
Logo Samsung semiconductor
Description 4M x 16Bit x 4 Banks Mobile SDRAM
Datasheet K4M56163PG DatasheetK4M56163PG Datasheet (PDF)

www.DataSheet4U.com K4M56163PG - R(B)E/G/C/F 4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 1.8V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Speci.

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www.DataSheet4U.com K4M56163PG - R(B)E/G/C/F 4M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA FEATURES • 1.8V power supply. • LVCMOS compatible with multiplexed address. • Four banks operation. • MRS cycle with address key programs. -. CAS latency (1, 2 & 3). -. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave). • EMRS cycle with address key programs. • All inputs are sampled at the positive going edge of the system clock. • Burst read single-bit write operation. • Special Function Support. -. PASR (Partial Array Self Refresh). -. Internal TCSR (Temperature Compensated Self Refresh) -. DS (Driver Strength) -. DPD (Deep Power Down) • DQM for masking. • Auto refresh. • • • • 64ms refresh period (8K cycle) Commercial Temperature Operation (-25°C ~ 70°C). Extended Temperature Operation (-25°C ~ 85°C). 54Balls FBGA ( -RXXX -Pb, -BXXX -Pb Free). Mobile SDRAM GENERAL DESCRIPTION The K4M56163PG is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x 4,196,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications. ORDERING INFORMATION Part No. K4M56163PG-R(B)E/G/C/F75 K4M56163PG-R(B)E/G/C/F90 K4M56163PG-R(B)E/G/C/F1L Max Freq. 133MHz(CL3), 83MHz(CL2) 111MHz(CL3), 83MHz(CL2) 111MHz(CL3)*1, 66MHz(CL2) LVCMOS 54 FBGA Pb (Pb Free) Interface Package - R(B)E/G : Normal/ Low Power, Extended Temperature(-25°C ~ 85°C) - R(B)C/F : Normal/ Low Power, Commercial Temperature(-25°C ~ 70°C) Notes : 1. In case of 40MHz Frequency, CL1 can be supported. Address configuration Organization 16M x 16 Bank BA0, BA1 Row A0 - A12 Column Address A0 - A8 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE CONSTRUED AS GRANTING ANY LICENSE, EXPRESS OR IMPLIED, BY ESTOPPEL OR OTHERWISE, TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND. 1. For updates or additional information about Samsung products, contact your nearest Samsung office. 2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply. February 2006 K4M56163PG - R(B)E/G/C/F FUNCTIONAL BLOCK DIAGRAM Mobile SDRAM I/O Control LWE Data Input Register Bank Select LDQM 4M x 16 Sense AMP 4M x 16 4M x 16 4M x 16 Refresh Counter Output Buffer Row Decoder Row Buffer DQi Address Register LRAS CLK CKE CLK ADD Column Decoder Col. Buffer LRAS LCBR Latency & Burst Length LCKE LCBR LWE LCAS Programming Register LWCBR LDQM Timing Register CS RAS CAS WE L(U)DQM February 2006 K4M56163PG - R(B)E/G/C/F Package Dimension and Pin Configuration < Bottom View*1 > E1 Mobile SDRAM < Top View*2 > 54Ball(6x9) FBGA 9 A B C D1 D E F G H J D e 8 7 6 5 4 3 2 1 A B C D E F G H J 1 VSS DQ14 DQ12 DQ10 DQ8 UDQM A12 A8 VSS 2 DQ15 DQ13 DQ11 DQ9 NC CLK A11 A7 A5 3 VSSQ VDDQ VSSQ VDDQ VSS CKE A9 A6 A4 7 VDDQ VSSQ VDDQ VSSQ VDD CAS BA0 A0 A3 8 DQ0 DQ2 DQ4 DQ6 LDQM RAS BA1 A1 A2 9 VDD DQ1 DQ3 DQ5 DQ7 WE CS A10 VDD E Pin Name CLK CS CKE A A1 b A0 ~ A12 BA0 ~ BA1 RAS CAS WE L(U)DQM Pin Function System Clock Chip Select Clock Enable Address Bank Select Address Row Address Strobe Column Address Strobe Write Enable Data Input/Output Mask Data Input/Output Power Supply/Ground Data Output Power/Ground [Unit:mm] z < Top View*2 > #A1 Ball Origin Indicator DQ0 ~ 15 VDD/VSS VDDQ/VSSQ SEC Week XXXX K4M56163PG Symbol A A1 E E1 D D1 e b z Min 0.25 7.9 10.9 0.45 - Typ 8.0 6.40 11.0 6.40 0.80 0.50 - Max 1.00 8.1 11.1 0.55 0.10 February 2006 K4M56163PG - R(B)E/G/C/F ABSOLUTE MAXIMUM RATINGS Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 2.6 -1.0 ~ 2.6 -55 ~ +150 1.0 50 Mobile SDRAM Unit V V °C W mA NOTES: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. DC OPERATING CONDITIONS Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25°C ~ 85°C for Extended, -25°C ~ 70°C for Commercial) Parameter Supply voltage VDDQ Input logic high voltage Input l.


ISL3684 K4M56163PG KP-1608SYC


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