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ICS554-01A
LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
Description
The ICS554-01A is a low skew clock buffer with a single complimentary PECL input to four PECL outputs. Part of ICS’ Clock BlocksTM family, this is our lowest skew PECL clock buffer. The ICS554-01A is footprint compatible with the ICS554-01, but requires fewer passive components for termination thus providing a cost-saving alternative. For parts which do not require PECL inputs or outputs, see the ICS553 for a 1 to 4 low skew buffer, or the ICS552-02 for a 1 to 8 low skew buffer. For more than 8 outputs see the MK74CBxxx BuffaloTM series of clock drivers. ICS makes many non-PLL and PLL based low skew output devices as well as Zero Delay Buffers to synchronize clocks. Contact us for all of your clocking needs.
Features
• • • • • • • • •
Input frequency up to 200 MHz Advanced CMOS process Outputs are skew matched to within 50 ps Packaged in 16-pin TSSOP One PECL input to 4 PECL output clock drivers Operating Voltages of 3.3 V or 5 V Industrial temperature range Functional equivalent to ICS554-01 Simplified passive termination network compared to ICS554-01
Block Diagram
VDD IN IN Q0 Q0
Q1 Q1
Q2 Q2
Q3 Q3 VSS
MDS 554-01A A I n t e gra te d C i r c u i t S y s t e m s
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1
525 Race Stre et, San Jo se, CA 9 5126
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Revision 101904 te l (40 8) 2 97-12 01
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w w w. i c st . c o m
ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
Pin Assignment
NC VDD Q0 Q0 Q1 Q1 GND IN 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 NC VDD Q3 Q3 Q2 Q2 GND IN
16-pin 173 mil (0.65mm) TSSOP
Pin Descriptions
Number
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
Name
NC VDD Q0 Q0 Q1 Q1 GND IN IN GND Q2 Q2 Q3 Q3 VDD NC
Type
— Power Output Output Output Output Power Input Input Power Output Output Output Output Power — No Connect.
Pin Description
Connect to +3.3 V or 5 V. Must be same as pin 15. Clock Output Q0. Clock Output Q0. Clock Output Q1. Clock Output Q1. Connect to Ground. PECL Clock Input. Complementary PECL Clock Input. Connect to Ground Clock Output Q2. Clock Output Q2. Clock Output Q3. Clock Output Q3. Connect to +3.3 V or 5 V. Must be same as pin 2. No Connect.
MDS 554-01A A In te grated Circuit Systems
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2
525 Ra ce Street, San Jose, CA 9512 6
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Revision 101904 tel (4 08) 297-1 201
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w w w. i c s t . c o m
ICS554-01A LOW SKEW 1 TO 4 CLOCK BUFFER PECL IN, PECL OUT
External Components
The ICS554-01A requires a decoupling capacitor of 0.01µF to be connected between VDD on pin 2 and GND on pin 7, as well as between VDD on pin 15 and GND on pin 10. These decoupling capacitors should be placed as close to the device as possible. To achieve the low output skews that the ICS554-01A is capable of, careful attention must be paid to board layout. Essentially, all 8 outputs must have identical terminations, loads, and trace geometries. If they do not, the output skew will be degraded. For example, using a 30Ω series termination on one output (with 33Ω on the others) will cause a.