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ZL30117 Dataheets PDF



Part Number ZL30117
Manufacturers Zarlink Semiconductor
Logo Zarlink Semiconductor
Description SONET/SDH Low Jitter Line Card Synchronizer
Datasheet ZL30117 DatasheetZL30117 Datasheet (PDF)

www.DataSheet4U.com ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet February 2006 A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30117GGG 64 Pin CABGA Trays ZL30117GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 sync inputs for.

  ZL30117   ZL30117


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www.DataSheet4U.com ZL30117 SONET/SDH Low Jitter Line Card Synchronizer Data Sheet February 2006 A full Design Manual is available to qualified customers. To register, please send an email to [email protected]. Ordering Information ZL30117GGG 64 Pin CABGA Trays ZL30117GGG2 64 Pin CABGA* Trays *Pb Free Tin/Silver/Copper -40oC to +85oC • Provides 3 reference inputs which support clock frequencies with any multiples of 8 kHz up to 77.76 MHz in addition to 2 kHz Provides 3 sync inputs for output frame pulse alignment Generates several styles of output frame pulses with selectable pulse width, polarity, and frequency Configurable input to output delay, and output to output phase alignment Flexible input reference monitoring automatically disqualifies references based on frequency and phase irregularities Supports IEEE 1149.1 JTAG Boundary Scan Features • Synchronizes with standard telecom system references and synthesizes a wide variety of protected telecom line interface clocks that are compliant with Telcordia GR-253-CORE and ITU-T G.813 Internal APLL provides standard output clock frequencies from 6.48 MHz up to 622.08 MHz with jitter less than 1 ps RMS for OC-48/STM-16 interfaces Programmable output synthesizer generates clock frequencies from any multiple of 8 kHz up to 77.76 MHz in addition to 2 kHz Digital Phase Locked-Loop (DPLL) provides all the features necessary for generating SONET/SDH compliant clocks including automatic hitless reference switching, automatic mode selection (locked, free-run, holdover), and selectable loop bandwidth • • • • • • • • trst_b tck tdi tms tdo dpll_lock dpll_holdover diff_en osco osci Master Clock IEEE 1449.1 JTAG ref0 ref1 ref2 ref2:0 ref diff_clk_p/n SONET/SDH APLL sdh_clk sdh_fp p_clk p_fp DPLL sync0 sync1 sync2 sync2:0 Reference Monitors ref_&_sync_status sync Programmable Synthesizer int_b SPI Interface Controller & State Machine sck si so cs_b rst_b dpll_mod_sel sdh_filter filter_ref0 filter_ref1 Figure 1 - Block Diagram 1 Zarlink Semiconductor Inc. Zarlink, ZL and the Zarlink Semiconductor logo are trademarks of Zarlink Semiconductor Inc. Copyright 2006, Zarlink Semiconductor Inc. All Rights Reserved. www.DataSheet4U.com ZL30117 Applications • • • • • • AMCs for AdvancedTCATM and MicroTCA Systems Multi-Service Edge Switches or Routers DSLAM Line Cards WAN Line Cards RNC/Mobile Switching Center Line Cards ADM Line Cards Data Sheet 2 Zarlink Semiconductor Inc. www.DataSheet4U.com ZL30117 Table of Contents Data Sheet 1.0 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.1 DPLL Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 1.2 DPLL Mode Of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 1.3 Ref and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 1.4 Ref and Sync Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 1.5 Output Clocks and Frame Pulses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 1.6 Configurable Input-to-Output and Output-to-Output Delays . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 2.0 Software Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 3.0 References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 3 Zarlink Semiconductor Inc. www.DataSheet4U.com ZL30117 List of Figures Data Sheet Figure 1 - Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Figure 2 - Automatic Mode State Machine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Figure 3 - Reference and Sync Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 4 - Output Frame Pulse Alignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Figure 5 - Behaviour of the Guard Soak Timer during CFM or SCM Failures . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Figure 6 - Output Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7 - Phase Delay Adjustments . . . . ..


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