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AD9233 Dataheets PDF



Part Number AD9233
Manufacturers Analog Devices
Logo Analog Devices
Description 1.8V Analog-to-Digital Converter
Datasheet AD9233 DatasheetAD9233 Datasheet (PDF)

12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter AD9233 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.15 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock duty cycle stabilizer Data o.

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12-Bit, 80 MSPS/105 MSPS/125 MSPS, 1.8 V Analog-to-Digital Converter AD9233 FEATURES 1.8 V analog supply operation 1.8 V to 3.3 V output supply SNR = 69.5 dBc (70.5 dBFS) to 70 MHz input SFDR = 85 dBc to 70 MHz input Low power: 395 mW @ 125 MSPS Differential input with 650 MHz bandwidth On-chip voltage reference and sample-and-hold amplifier DNL = ±0.15 LSB Flexible analog input: 1 V p-p to 2 V p-p range Offset binary, Gray code, or twos complement data format Clock duty cycle stabilizer Data output clock Serial port control Built-in selectable digital test pattern generation Programmable clock and data alignment APPLICATIONS Ultrasound equipment IF sampling in communications receivers IS-95, CDMA-One, IMT-2000 Battery-powered instruments Hand-held scopemeters Low cost digital oscilloscopes GENERAL DESCRIPTION The AD9233 is a monolithic, single 1.8 V supply, 12-bit, 80 MSPS/ 105 MSPS/125 MSPS analog-to-digital converter (ADC), featuring a high performance sample-and-hold amplifier (SHA) and onchip voltage reference. The product uses a multistage differential pipeline architecture with output error correction logic to provide 12-bit accuracy at 125 MSPS data rates and guarantees no missing codes over the full operating temperature range. The wide bandwidth, truly differential SHA allows a variety of user-selectable input ranges and offsets, including single-ended applications. It is suitable for multiplexed systems that switch full-scale voltage levels in successive channels and for sampling single-channel inputs at frequencies well beyond the Nyquist rate. Combined with power and cost savings over previously available ADCs, the AD9233 is suitable for applications in communications, imaging, and medical ultrasound. A differential clock input controls all internal conversion cycles. A duty cycle stabilizer (DCS) compensates for wide variations in the clock duty cycle while maintaining excellent overall ADC performance. Rev. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. 05492-001 VIN+ VIN– REFT REFB VREF SENSE FUNCTIONAL BLOCK DIAGRAM AVDD DRVDD AD9233 SHA MDAC1 8-STAGE 1 1/2-BIT PIPELINE A/D 4 8 3 A/D CORRECTION LOGIC 13 OUTPUT BUFFERS REF SELECT 0.5V CLOCK DUTY CYCLE STABILIZER MODE SELECT OR DCO D11 (MSB) D0 (LSB) SCLK/DFS SDIO/DCS CSB AGND CLK+ CLK– Figure 1. PDWN DRGND The digital output data is presented in offset binary, Gray code, or twos complement formats. A data output clock (DCO) is provided to ensure proper latch timing with receiving logic. The AD9233 is available in a 48-lead L.


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