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74ALVCHT16835 18-bit registered driver (3-State)
Product data 2002 Jun 05
Philips Semiconductors
Philips Semiconductors
Product data
18-bit registered driver (3-State)
74ALVCHT16835
FEATURES
• Wide supply voltage range of 2.3 V to 3.6 V • Complies with JEDEC standard no. 8-1A. • CMOS low power consumption • Direct interface with TTL levels • Current drive ± 24 mA at 3.0 V • MULTIBYTETM flow-through standard pin-out architecture • Low inductance multiple VCC and GND pins for minimum noise
and ground bounce
PIN CONFIGURATION
NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CP GND
• Output drive capability 50 Ω transmission lines @ 85 °C • ESD protection exceeds 1500 V HBM per JESD22-A114, A115
and 1000 V CDM per JESD22-C101
• Bus hold on data inputs eliminates the need for external
pullup/pulldown resistors
DESCRIPTION
The 74ALVCHT16835 is a 18-bit registered driver. Data flow is controlled by active low output enable (OE), active high latch enable (LE) and clock inputs (CP). When LE is HIGH, the A to Y data flow is transparent. When LE is LOW and CP is held at LOW or HIGH, the data is latched; on the LOW to HIGH transient of CP the A-data is stored in the latch/flip-flop. When OE is LOW the outputs are active. When OE is HIGH, the outputs go to the high impedance OFF-state. Operation of the OE input does not affect the state of the latch/flip-flop. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE
SH00188
QUICK REFERENCE DATA
GND = 0 V; Tamb = 25 °C; tr = tf ≤ 2.5 ns SYMBOL tPHL/tPLH fmax CI CI/O PARAMETER Propagation delay An to Yn; LE to Yn; CP to Yn Maximum clock frequency Input capacitance Input/Output capacitance transparent mode Output enabled Output disabled Clocked mode Output enabled Output disabled CONDITIONS VCC = 3.3 V, CL = 50 pF VCC = 3.3 V, CL = 50 pF TYPICAL 2.3 2.7 2.2 350 4.0 8.0 13 3 22 15 UNIT ns MHz pF pF
CPD
Power dissipation capacitance per buffer
VI = GND to VCC1
pF
NOTES: 1. CPD is used to determine the dynamic power dissipation (PD in µW): PD = CPD × VCC2 × fi + S (CL × VCC2 × fo) where: fi = input frequency in MHz; CL = output load capacitance in pF; fo = output frequency in MHz; VCC = supply voltage in V; S (CL × VCC2 × fo) = sum of outputs.
2002 Jun 05
2
853-2350 28376
Philips Semiconductors
Product data
18-bit registered driver (3-State)
74ALVCHT16835
ORDERING INFORMATION
PACKAGES 56-Pin Plastic TSSOP (TVSOP), 0.4 mm pitch TEMPERATURE RANGE –40 to +85 °C ORDER CODE 74ALVCHT16835DGV DRAWING NUMBER SOT481-2
PIN DESCRIPTION
PIN NUMBER 1, 2, 55 3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26 4, 11, 18, 25, 29, 32, 39, 46, 53, 56 7, 22, 35, 50 27 28 30 54, 52, 51, 49, 48, 47, 45, 44, 43, 42, 41, 40, 38, 37, 36, 34, 33, 31 SYMBOL NC Y1 to Y18 GND VCC OE LE CP A1 to A18 NAME AND FUNCTION No connection Data outputs
LOGIC SYMBOL
OE
Ground (0 V)
CP
Positive supply voltage Output enable input (active LOW) Latch enable input Clock input Data inputs
A1 D LE CP Y1 LE
TO THE 17 OTHER CHANNELS
SH00203
2002 Jun 05
3
Philips Semiconductors
Product data
18-bit registered driver (3-State)
74ALVCHT16835
LOGIC SYMBOL (IEEE/IEC)
OE CP LE 27 30 28 G7 EN5 3C4
FUNCTION TABLE
INPUTS OE H L L L L L L H L X Z ↑ = = = = = LE X H H L L L L CP X X X ↑ ↑ H L A X L H L H X X OUTPUTS Z L H L H Y01 Y02
Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18
3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 25
4D
1, 2 ∇
54 52 51 49 48 47 45 44 43 42
A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18
HIGH voltage level LOW voltage level Don’t care High impedance “off” state LOW-to-HIGH level transition
8D
5, 6 ∇
41 40 38 37 36 34 33 31
NOTES: 1. Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. 2. Output level before the indicated steady-state input conditions were established.
SH00190
2002 Jun 05
4
Philips Semiconductors
Product data
18-bit registered driver (3-State)
74ALVCHT16835
RECOMMENDED OPERATING CONDITIONS
SYMBOL PARAMETER DC supply voltage 2.5 V range (for max. speed performance @ 30 pF output load) VCC DC supply voltage 3.3 V range (for max. speed performance @ 50 pF output load) DC supply voltage (for low-voltage applications) VI VO Tamb tr, tf DC Input voltage range DC output voltage range Operating free-air temperature range Input rise and fall times VCC = 2.3 to 3.0 V VCC = 3.0 to 3.6 V CONDITIONS MIN 2.3 3.0 2.3 0 0 –40 0 0 MAX 2.7 .