Document
www.DataSheet4U.com
NB3N3001
3.3 V 106.25 MHz/ 212.5 MHz PureEdge Clock Generator with LVPECL Differential Output
Description
The NB3N3001 is a low−jitter, dual−rate PLL−synthesized clock generator. It accepts a standard 26.5625 MHz fundamental mode AT cut parallel resonant crystal as the reference source for its integrated crystal oscillator and low noise phase−locked loop (PLL) and produces user selectable clock frequencies of either 106.25 MHz or 212.5 MHz. In addition, the PLL circuitry will generate a 50% duty cycle square−wave through a pair of differential LVPECL clock outputs. Typical phase jitter at 106.25 MHz is 0.3 ps RMS from 637 kHz to 10 MHz. The LVPECL output drivers can be disabled to high impedance with the OE pin set LOW. The NB3N3001 operates from a single +3.3 V supply, and is available in both plastic package and die form. The operating temperature range is from −40°C to +85°C. The NB3N3001 device provides the optimum combination of low cost, flexibility, and high performance which makes it ideal for Fibre−Channel applications.
Features
http://onsemi.com
MARKING DIAGRAM
301 YWW AG
TSSOP−8 DT SUFFIX CASE 948S
A Y WW G
= Assembly Location = Year = Work Week = Pb−Free Package
• • • • • • • •
• • • •
PureEdge Clock Family Provides Accuracy and Precision Selectable Output Frequency of 106.25 MHz or 212.5 MHz Crystal Oscillator Interface Designed for a 26.5625 MHz Crystal Fully Integrated Phase−Lock−Loop with Internal Loop Filter Differential 3.3 V LVPECL Outputs Exceeds Bellcore and ITU Jitter Generation Specification RMS Phase Jitter @ 106.25 MHz, using a 26.5625 MHz Crystal (637 kHz − 10 MHz): 0.3 ps (Typical) RMS Phase Noise at 106.25 MHz Phase Noise: Offset Noise Power 100 Hz −108 dBc/Hz 1 kHz −122 dBc/Hz 10 kHz −135 dBc/Hz 100 kHz −135 dBc/Hz Operating Range: VCC = 3.135 V to 3.465 V −40°C to +85°C Ambient Operating Temperature Small Footprint 8−pin TSSOP Package This is a Pb−Free Device
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 7 of this data sheet.
FSEL XIN 26.5625 MHz XOUT M = B32 Crystal Oscillator Phase Detector Charge Pump VCO 850 MHz N =B8 orB4 LVPECL Output
Q
212.5 MHz or Q 106.25 MHz
Figure 1. Logic Diagram
© Semiconductor Components Industries, LLC, 2006
1
October, 2006 − Rev. 1
Publication Order Number: NB3N3001/D
NB3N3001
VCCA 1 8 VCC
Table 1. Output Frequency Select
VEE 2 7 Q FSEL 0 6 Q 1 XIN 4 5 FSEL NOTE: Input crystal = 26.5625 MHz 212.5 Output Frequency (MHz) 106.25
NB3N3001
XOUT 3
Figure 2. Pinout (Top View) Table 2. PIN DESCRIPTION
Pin 1 2 3 4 5 6 7 8 Symbol VCCA VEE XOUT XIN FSEL Q Q VCC Type Power Power Input Input LVTTL/LVCMOS Input Output Output Power Description Positive analog power supply pin. Connected to VCC with filter components (See Figure 8). Negative supply pin. Crystal input (OUT). Crystal input (IN). Frequency select pin. Defaults LOW when left open. Internal pull down resistor to VEE. Inverted differe.