Document
MC100E310
5 V ECL Low Voltage 2:8
Differential Fanout Buffer
Description The MC100E310 is a low voltage, low skew 2:8 differential ECL
fanout buffer designed with clock distribution in mind. The device features fully differential clock paths to minimize both device and system skew. The E310 offers two selectable clock inputs to allow for redundant or test clocks to be incorporated into the system clock trees.
The lowest TPD delay time results from terminating only one output pair, and the greatest TPD delay time results from terminating all the output pairs. This shift is about 10−20 pS in TPD. The skew between any two output pairs within a device is typically about 25 nS. If other output pairs are not terminated, the lowest TPD delay time results from both output pairs and the skew is typically 25 nS. When all outputs are terminated, the greatest TPD (delay time) occurs and all outputs display about the same 10−20 ps increase in TPD, so the relative skew between any two output pairs remains about 25 ns.
For more information on using PECL, designers should refer to ON Semiconductor Application Note AN1406/D.
The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open.
The 100 Series Contains Temperature Compensation.
Features
• Dual Differential Fanout Buffers
• 200 ps Part-to-Part Skew
• 50 ps Output-to-Output Skew
• 28-lead PLCC Packaging
• Q Output will Default LOW with Inputs Open or at VEE • PECL Mode Operating Range: VCC = 4.2 V to 5.7 V
with VEE = 0 V
• NECL Mode Operating Range: VCC = 0 V
with VEE = −4.2 V to −5.7 V
• Internal Input 50 kW Pulldown Resistors
• ESD Protection:
♦ > 2 kV Human Body Model ♦ > 200 V Machine Model
• Meets or Exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
• Moisture Sensitivity: Level 3 (Pb-Free)
(For Additional Information, see Application Note AND8003/D)
• Flammability Rating: UL 94 V−0 @ 0.125 in,
Oxygen Index: 28 to 34
• Transistor Count = 212 Devices
• These Devices are Pb-Free, Halogen Free and are RoHS Compliant
www.onsemi.com
PLCC−28 FN SUFFIX CASE 776−02
MARKING DIAGRAM* 1 28
MC100E310FNG AWLYYWW
A = Assembly Location WL = Wafer Lot YY = Year WW = Work Week G = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
Device
Package Shipping†
MC100E310FNG
PLCC−28 (Pb-Free)
37 Units / Tube
MC100E310FNR2G
PLCC−28 500 Tape & Reel (Pb-Free)
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
July, 2016 − Rev. 7
1
Publication Order Number: MC100E310/D
MC100E310
Q0 Q0 Q1 VCCO Q1 Q2 Q2
25 24 23 22 21 20 19
VEE 26
18
CLK_SEL 27
17
CLKa 28 VCC 1
CLKa 2
Pinout: 28-Lead PLCC (Top View)
16 15 14
VBB 3
13
CLKb 4
12
5 6 7 8 9 10 11
Q3 Q3 Q4 VCCO Q4 Q5 Q5
CLKb NC Q7 VCCO Q7 Q6 Q6
* All VCC and VCCO pins are tied together on the die. Warning: All VCC, VCCO, and VEE pins must be externally connected to Power Supply to guarantee proper operation. Figure 1. Logic Diagram and Pinout Assignment
CLKa CLKa CLKb CLKb
CLK_SEL
VBB Figure 2. Logic Symbol
Q0 Q0
Q1 Q1
Q2 Q2
Q3 Q3
Q4 Q4
Q5 Q5
Q6 Q6
Q7 Q7
Table 1. PIN DESCRIPTION
PIN Function
CLKa, CLKb; CLKa, CLKb Q0:7; Q0:7 CLK_SEL VBB VCC, VCCO VEE NC
ECL Differential Input Pairs ECL Differential Input Pairs ECL Differential Outputs ECL Input Clock Select Reference Voltage Output Positive Supply Negative Supply No Connect
Table 2. FUNCTION TABLE PIN Function 0 CLKa Selected 1 CLKb Selected
www.onsemi.com 2
MC100E310
Table 3. MAXIMUM RATINGS
Symbol
Parameter
Condition 1
Condition 2
Rating
Unit
VCC PECL Mode Power Supply VI PECL Mode Input Voltage
NECL Mode Input Voltage Iout Output Current
VEE = 0 V VEE = 0 V VCC = 0 V Continuous Surge
VI ≤ VCC VI ≥ VEE
8V 6V −6 V 50 mA 100 mA
IBB VBB Sink/Source
TA Operating Temperature Range
Tstg Storage Temperature Range
qJA
Thermal Resistance (Junction-to-Ambient) 0 lfpm 500 lfpm
PLCC−28 PLCC−28
±0.5 −40 to +85 −65 to +150
63.5 43.5
mA °C °C °C/W °C/W
qJC
Thermal Resistance (Junction-to-Case)
Standard Board
PLCC−28
Tsol Wave Solder (Pb-Free)
22 to 26 265
°C/W °C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed, damage may occur and reliability may be affected.
www.onsemi.com 3
MC100E310
Table 4. 100E SERIES PECL DC CHARACTERISTICS (VCCx = 5.0 V; VEE = 0 V (Note 1))
−40°C
25°C
85°C
Symbol
Characteristic
Min Typ Max Min Typ Max Min Typ Max Unit
IEE VOH VOL VIH VIL VBB VIHCMR
.