ADN2817

www.DataSheet4U.com Continuous Rate 12.3Mb/s to 2.7Gb/s Clock and Data Recovery ICs Preliminary Technical Data FEATURES Serial data input: 12.3 Mb/s to 2.7 Gb/s Exceeds ITU-T Jitter Specifications Integrated Limiting Amp: 6mV sensitivity (ADN2817 only) Adjustable slice level: ±100 mV (ADN2817 only) Patented dual-loop clock recovery architecture Programmable LOS detect (ADN2817 only) Slice level and sample phase adjustments (ADN2817 only) Integrated PRBS Generator and Detector No reference clock required Loss of lock indicator Supports Double Data Rate Relative Bit Error Rate Monitor Rate Selectivity without the use of a reference clock I2C™ interface to access optional features Single-supply operation: 3.3 V Low power: 650/600 mW (ADN2817/ADN2818) 5 mm × 5 mm 32-lead LFCSP ADN2817/ADN2818 PRODUCT DESCRIPTION The ADN2817/ADN2818 provides the receiver functions of quantization, signal level detect, and clock and data recovery for continuous data rates from 12.3 Mb/s to 2.7 Gb/s. The ADN2817/ADN2818 automatically locks to all data rates without the need for an external reference clock or programming. All SONET jitter requirements are exceeded, including jitter transfer, jitter generation, and jitter tolerance. All specifications are quoted for −40°C to +85°C ambient temperature, unless otherwise noted. This device, together with a PIN diode and a TIA preamplifier, can implement a highly integrated, low cost, low power fiber optic receiver. The ADN2817/ADN2818 have many optiona...